[PATCH] D114960: [AArch64][SVE] Lower shuffles to permute instructions: rev/revb/revh/revw

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

In D114960#3175627 <https://reviews.llvm.org/D114960#3175627>, @wwei wrote:

> @paulwalker-arm, could you help to review this patch and  D113376 <https://reviews.llvm.org/D113376>?

Sorry @wwei, I was hoping to review both patches today but that hasn't really worked out.  I'll take a proper look tomorrow.  One observation: The patch could do with some floating point tests to verify the `BITCAST` logic for those types.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:19322-19323
+        RevOp = AArch64ISD::REVW_MERGE_PASSTHRU;
+      Op = LowerToPredicatedOp(DAG.getNode(ISD::BITCAST, DL, NewVT, Op1), DAG,
+                               RevOp);
+      Op = DAG.getNode(ISD::BITCAST, DL, ContainerVT, Op);
----------------
Calling `LowerToPredicatedOp` feels like overkill here compared to `DAG.getNode(RevOp, DL, NewVT, ..., DAG.getUNDEF(NewVT)`


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  https://reviews.llvm.org/D114960/new/

https://reviews.llvm.org/D114960