[PATCH] D114856: [RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10095
+                                   SmallVectorImpl<SDNode *> &Created) const {
+  // only for Zbt.
+  if (!Subtarget.hasStdExtZbt())
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Capitalize 'only'


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10105
+  EVT VT = N->getValueType(0);
+  if ((VT != MVT::i32 && VT != MVT::i64) ||
+      !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
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Is i64 correct here for RV32? I don't see a test case.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10106
+  if ((VT != MVT::i32 && VT != MVT::i64) ||
+      !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
+    return SDValue();
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Use APInt::isNegatedPowerOf2


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Comment at: llvm/test/CodeGen/RISCV/rv32zbt-div-pow2.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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Can you add test cases for dividing by 2 and -2 as well? X86 does not use BuildSDIVPow2 for those cases so we should check those.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D114856/new/

https://reviews.llvm.org/D114856