[PATCH] D115244: [LICM] Promote conditional, loop-invariant memory accesses to scalars

[Djordje Todorovic via Phabricator via llvm-commits]

djtodoro added a comment.

Thanks for working on this! This looks like an addition to https://reviews.llvm.org/D113289.

Can you please simplify the summary (e.g. the IR code could be written in a pseudo IR) ?



================
Comment at: llvm/lib/Transforms/Scalar/LICM.cpp:145
+// them.
+cl::opt<bool> SetLicmConditionalAccessPromotion(
+    "licm-conditional-access-promotion", cl::Hidden, cl::init(false),
----------------
IIUC, this should be target-independent optimization? And, GCC generates such code for both x86_64 and aarch64, right?

The generated code will be bigger, so this will impact the code size, so I guess this needs motivation in terms of (SPEC) benchmarking.


================
Comment at: llvm/lib/Transforms/Scalar/LICM.cpp:1959
+          MSSAU->getMemorySSA()->verifyMemorySSA();
+        // Update the LoopInsertPts[i].
+        LoopInsertPts[i] = &*ExitBlock->getFirstInsertionPt();
----------------
This is comment is redundant.


================
Comment at: llvm/test/Transforms/LICM/conditional-access-promotion.ll:13-16
+; ModuleID = 'test-case.c'
+source_filename = "test-case.c"
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64"
----------------
not needed


================
Comment at: llvm/test/Transforms/LICM/conditional-access-promotion.ll:88-106
+attributes #0 = { nounwind uwtable "frame-pointer"="non-leaf" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+neon,+v8a" }
+
+!llvm.module.flags = !{!0, !1, !2, !3, !4, !5, !6}
+!llvm.ident = !{!7}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, !"branch-target-enforcement", i32 0}
----------------
I guess we don't need these.


Repository:
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  https://reviews.llvm.org/D115244/new/

https://reviews.llvm.org/D115244