[llvm] 2925f3c - [X86] LowerRotate - pull out repeated splitVectorIntBinary call. NFC.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-12-07T12:05:33Z
New Revision: 2925f3c9ae1beb49ee37b745bbed2ad6ed3d8d27

URL: https://github.com/llvm/llvm-project/commit/2925f3c9ae1beb49ee37b745bbed2ad6ed3d8d27
DIFF: https://github.com/llvm/llvm-project/commit/2925f3c9ae1beb49ee37b745bbed2ad6ed3d8d27.diff

LOG: [X86] LowerRotate - pull out repeated splitVectorIntBinary call. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 660cf626946b..8838faf0032e 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -29820,12 +29820,14 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
 
   assert(IsROTL && "Only ROTL supported");
 
+  // Split 256-bit integers on XOP/pre-AVX2 targets.
+  if (VT.is256BitVector() && (Subtarget.hasXOP() || !Subtarget.hasAVX2()))
+    return splitVectorIntBinary(Op, DAG);
+
   // XOP has 128-bit vector variable + immediate rotates.
   // +ve/-ve Amt = rotate left/right - just need to handle ISD::ROTL.
   // XOP implicitly uses modulo rotation amounts.
   if (Subtarget.hasXOP()) {
-    if (VT.is256BitVector())
-      return splitVectorIntBinary(Op, DAG);
     assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
 
     // Attempt to rotate by immediate.
@@ -29839,10 +29841,6 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
     return Op;
   }
 
-  // Split 256-bit integers on pre-AVX2 targets.
-  if (VT.is256BitVector() && !Subtarget.hasAVX2())
-    return splitVectorIntBinary(Op, DAG);
-
   assert((VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8 ||
           ((VT == MVT::v8i32 || VT == MVT::v16i16 || VT == MVT::v32i8) &&
            Subtarget.hasAVX2()) ||