[PATCH] D113798: Add loop unrolling and peeling preferences for RISCV

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

Sorry, I missed the previous ping and was out last week:

- @luismarques reports this is performance neutral for Embench and Coremark on Ibex.
- Representative benchmarks for anything like this is clearly difficult. If anyone has run e.g. SPEC on real RISC-V hardware, that would be interesting. Cases where the change is roughly performance neutral but may waste I$ might not show up on simple benchmarks.
- Just as another datapoint, I ran this against the GCC torture suite. One case that stuck out to me was pr85169.c. It seems pretty unlikely that huge number of unrolled stores of zero byte is profitable (though maybe my intuition is wrong!). Could you please take a quick look at this case to see if there is any obvious tuning that can be done for it?

Otherwise, this looks good to me, and I don't think pr85169.c needs to be a blocker.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113798/new/

https://reviews.llvm.org/D113798