[PATCH] D115166: [AArch64][SVE] Fix fptrunc store for fixed len vector

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm created this revision.
peterwaller-arm added reviewers: bsmith, MattDevereau, DavidTruby, paulwalker-arm, efriedma.
Herald added subscribers: psnobl, hiraditya, kristof.beyls, tschuett.
peterwaller-arm requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Restrict duplicate FP_EXTEND/FP_TRUNC -> LOAD/STORE DAG combines to only
larger than NEON types, as these are the ones for which there is custom
lowering.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D115166

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fpext-load.ll
  llvm/test/CodeGen/AArch64/sve-fptrunc-store.ll


Index: llvm/test/CodeGen/AArch64/sve-fptrunc-store.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-fptrunc-store.ll
+++ llvm/test/CodeGen/AArch64/sve-fptrunc-store.ll
@@ -85,3 +85,16 @@
   store <vscale x 8 x half> %1, <vscale x 8 x half>* %dst, align 2
   ret void
 }
+
+; Fixed length vector regression test.
+define void @fptrunc_v2f64_v2f32(<2 x double> %val, <2 x float>* %ptr) {
+; CHECK-LABEL: fptrunc_v2f64_v2f32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtn v0.2s, v0.2d
+; CHECK-NEXT:    str d0, [x0]
+; CHECK-NEXT:    ret
+entry:
+  %trunc = fptrunc <2 x double> %val to <2 x float>
+  store <2 x float> %trunc, <2 x float>* %ptr
+  ret void
+}
Index: llvm/test/CodeGen/AArch64/sve-fpext-load.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-fpext-load.ll
+++ llvm/test/CodeGen/AArch64/sve-fpext-load.ll
@@ -83,3 +83,15 @@
   %load.ext = fpext <vscale x 4 x float> %load to <vscale x 4 x double>
   ret <vscale x 4 x double> %load.ext
 }
+
+; Fixed length vector regression test.
+define <2 x double> @ext_v2f32_v2f64(<2 x float>* %ptr) {
+; CHECK-LABEL: ext_v2f32_v2f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x0]
+; CHECK-NEXT:    fcvtl v0.2d, v0.2s
+; CHECK-NEXT:    ret
+  %load = load <2 x float>, <2 x float>* %ptr
+  %load.ext = fpext <2 x float> %load to <2 x double>
+  ret <2 x double> %load.ext
+}
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -15985,7 +15985,9 @@
   if (DCI.isBeforeLegalizeOps() && Value.getOpcode() == ISD::FP_ROUND &&
       Value.getNode()->hasOneUse() && ST->isUnindexed() &&
       Subtarget->useSVEForFixedLengthVectors() &&
-      Value.getValueType().isFixedLengthVector())
+      Value.getValueType().isFixedLengthVector() &&
+      Value.getValueType().getFixedSizeInBits() >
+          Subtarget->getMinSVEVectorSizeInBits())
     return DAG.getTruncStore(Chain, SDLoc(N), Value.getOperand(0), Ptr,
                              ST->getMemoryVT(), ST->getMemOperand());
 
@@ -17346,7 +17348,8 @@
   // they can be split down into something legal.
   if (DCI.isBeforeLegalizeOps() && ISD::isNormalLoad(N0.getNode()) &&
       N0.hasOneUse() && Subtarget->useSVEForFixedLengthVectors() &&
-      VT.isFixedLengthVector()) {
+      VT.isFixedLengthVector() &&
+      VT.getFixedSizeInBits() > Subtarget->getMinSVEVectorSizeInBits()) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
                                      LN0->getChain(), LN0->getBasePtr(),


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