[llvm] d8495e0 - [ARM] Add a vrinta.f16.f16 alias

[David Green via llvm-commits]

Author: David Green
Date: 2021-12-06T11:06:25Z
New Revision: d8495e03529201e8af9abeab05a3f671d0249041

URL: https://github.com/llvm/llvm-project/commit/d8495e03529201e8af9abeab05a3f671d0249041
DIFF: https://github.com/llvm/llvm-project/commit/d8495e03529201e8af9abeab05a3f671d0249041.diff

LOG: [ARM] Add a vrinta.f16.f16 alias

The v8.1-m ARMARM uses the vrinta.f16.f16 names, as opposed to
vrinta.f16. This adds an alias for it in the same way that we have for
f32 and f64.

Differential Revision: https://reviews.llvm.org/D68127

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMInstrVFP.td
    llvm/test/MC/ARM/fullfp16-neg.s
    llvm/test/MC/ARM/fullfp16.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td
index 9d1bfa414dff7..dc5f1b92a6c2b 100644
--- a/llvm/lib/Target/ARM/ARMInstrVFP.td
+++ b/llvm/lib/Target/ARM/ARMInstrVFP.td
@@ -1076,6 +1076,9 @@ multiclass vrint_inst_anpm<string opc, bits<2> rm,
     }
   }
 
+  def : InstAlias<!strconcat("vrint", opc, ".f16.f16\t$Sd, $Sm"),
+                  (!cast<Instruction>(NAME#"H") HPR:$Sd, HPR:$Sm), 0>,
+        Requires<[HasFullFP16]>;
   def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
                   (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>,
         Requires<[HasFPARMv8]>;

diff  --git a/llvm/test/MC/ARM/fullfp16-neg.s b/llvm/test/MC/ARM/fullfp16-neg.s
index 7069cbc61768f..753be4d1c10b9 100644
--- a/llvm/test/MC/ARM/fullfp16-neg.s
+++ b/llvm/test/MC/ARM/fullfp16-neg.s
@@ -123,24 +123,38 @@
 @ CHECK: instruction requires: full half-float
 
   vrintz.f16 s3, s24
+  vrintz.f16.f16 s3, s24
+@ CHECK: instruction requires: full half-float
 @ CHECK: instruction requires: full half-float
 
   vrintr.f16 s0, s9
+  vrintr.f16.f16 s0, s9
+@ CHECK: instruction requires: full half-float
 @ CHECK: instruction requires: full half-float
 
   vrintx.f16 s10, s14
+  vrintx.f16.f16 s10, s14
+@ CHECK: instruction requires: full half-float
 @ CHECK: instruction requires: full half-float
 
   vrinta.f16 s12, s1
+  vrinta.f16.f16 s12, s1
+@ CHECK: instruction requires: full half-float
 @ CHECK: instruction requires: full half-float
 
   vrintn.f16 s12, s1
+  vrintn.f16.f16 s12, s1
+@ CHECK: instruction requires: full half-float
 @ CHECK: instruction requires: full half-float
 
   vrintp.f16 s12, s1
+  vrintp.f16.f16 s12, s1
+@ CHECK: instruction requires: full half-float
 @ CHECK: instruction requires: full half-float
 
   vrintm.f16 s12, s1
+  vrintm.f16.f16 s12, s1
+@ CHECK: instruction requires: full half-float
 @ CHECK: instruction requires: full half-float
 
   vfma.f16 s2, s7, s4

diff  --git a/llvm/test/MC/ARM/fullfp16.s b/llvm/test/MC/ARM/fullfp16.s
index 4603b740d3ae2..d9149ee150e7d 100644
--- a/llvm/test/MC/ARM/fullfp16.s
+++ b/llvm/test/MC/ARM/fullfp16.s
@@ -169,31 +169,52 @@
 @ THUMB: vminnm.f16 s0, s0, s12    @ encoding: [0x80,0xfe,0x46,0x09]
 
   vrintz.f16 s3, s24
+  vrintz.f16.f16 s3, s24
 @ ARM:   vrintz.f16 s3, s24     @ encoding: [0xcc,0x19,0xf6,0xee]
+@ ARM:   vrintz.f16 s3, s24     @ encoding: [0xcc,0x19,0xf6,0xee]
+@ THUMB: vrintz.f16 s3, s24     @ encoding: [0xf6,0xee,0xcc,0x19]
 @ THUMB: vrintz.f16 s3, s24     @ encoding: [0xf6,0xee,0xcc,0x19]
 
   vrintr.f16 s0, s9
+  vrintr.f16.f16 s0, s9
 @ ARM:   vrintr.f16 s0, s9      @ encoding: [0x64,0x09,0xb6,0xee]
+@ ARM:   vrintr.f16 s0, s9      @ encoding: [0x64,0x09,0xb6,0xee]
+@ THUMB: vrintr.f16 s0, s9      @ encoding: [0xb6,0xee,0x64,0x09]
 @ THUMB: vrintr.f16 s0, s9      @ encoding: [0xb6,0xee,0x64,0x09]
 
   vrintx.f16 s10, s14
+  vrintx.f16.f16 s10, s14
 @ ARM:   vrintx.f16 s10, s14  @ encoding: [0x47,0x59,0xb7,0xee]
+@ ARM:   vrintx.f16 s10, s14  @ encoding: [0x47,0x59,0xb7,0xee]
+@ THUMB: vrintx.f16 s10, s14  @ encoding: [0xb7,0xee,0x47,0x59]
 @ THUMB: vrintx.f16 s10, s14  @ encoding: [0xb7,0xee,0x47,0x59]
 
   vrinta.f16 s12, s1
+  vrinta.f16.f16 s12, s1
+@ ARM:   vrinta.f16 s12, s1    @ encoding: [0x60,0x69,0xb8,0xfe]
 @ ARM:   vrinta.f16 s12, s1    @ encoding: [0x60,0x69,0xb8,0xfe]
+@ THUMB: vrinta.f16 s12, s1    @ encoding: [0xb8,0xfe,0x60,0x69]
 @ THUMB: vrinta.f16 s12, s1    @ encoding: [0xb8,0xfe,0x60,0x69]
 
   vrintn.f16 s12, s1
+  vrintn.f16.f16 s12, s1
+@ ARM:   vrintn.f16 s12, s1    @ encoding: [0x60,0x69,0xb9,0xfe]
 @ ARM:   vrintn.f16 s12, s1    @ encoding: [0x60,0x69,0xb9,0xfe]
+@ THUMB: vrintn.f16 s12, s1    @ encoding: [0xb9,0xfe,0x60,0x69]
 @ THUMB: vrintn.f16 s12, s1    @ encoding: [0xb9,0xfe,0x60,0x69]
 
   vrintp.f16 s12, s1
+  vrintp.f16.f16 s12, s1
+@ ARM:   vrintp.f16 s12, s1    @ encoding: [0x60,0x69,0xba,0xfe]
 @ ARM:   vrintp.f16 s12, s1    @ encoding: [0x60,0x69,0xba,0xfe]
+@ THUMB: vrintp.f16 s12, s1    @ encoding: [0xba,0xfe,0x60,0x69]
 @ THUMB: vrintp.f16 s12, s1    @ encoding: [0xba,0xfe,0x60,0x69]
 
   vrintm.f16 s12, s1
+  vrintm.f16.f16 s12, s1
+@ ARM:   vrintm.f16 s12, s1    @ encoding: [0x60,0x69,0xbb,0xfe]
 @ ARM:   vrintm.f16 s12, s1    @ encoding: [0x60,0x69,0xbb,0xfe]
+@ THUMB: vrintm.f16 s12, s1    @ encoding: [0xbb,0xfe,0x60,0x69]
 @ THUMB: vrintm.f16 s12, s1    @ encoding: [0xbb,0xfe,0x60,0x69]
 
   vfma.f16 s2, s7, s4