[PATCH] D115047: [SVE][InstCombine] Support more cases where ld1/st1 can be lowered to load instructions.

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau accepted this revision.
MattDevereau added a comment.
This revision is now accepted and ready to land.

lgtm, theres an error in a comment



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Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:735
+    // If the predicate has the same or less lanes than the uncasted
+    // predicate then we know the casting has no affect.
+    if (cast<ScalableVectorType>(Pred->getType())->getMinNumElements() <=
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https://reviews.llvm.org/D115047