[PATCH] D114586: [VPlan] Verify plan entry and exit blocks, set correct exit block.

[Ayal Zaks via Phabricator via llvm-commits]

Ayal accepted this revision.
Ayal added a comment.
This revision is now accepted and ready to land.

This is fine! Adding a follow-up thought.



================
Comment at: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp:9633
 
+  cast<VPRegionBlock>(Plan->getEntry())->setExit(VPBB);
   // Now that sink-after is done, move induction recipes for optimized truncates
----------------
fhahn wrote:
> Ayal wrote:
> > Another way of fixing this would be to have split-blocks update Exit, when it updates VPBB?
> Yes, I can change it, but I think that be a bit more work.
(Continuing to reason about the above other way, independent of this patch which is fine - ) would it make sense to maintain a valid Region throughout, i.e., create it with an Entry and Exit upfront? That is, with a non-empty Entry following D111299, connected to an initially empty Exit, and where intra-loop code/blocks are to be introduced between VPBB and Exit (except for code seeking to be introduced in the latch/Exit..). Admittedly refers to D113182. Or would doing so interfere with how D111299 et al. seek to model/build the vector latch, preheader and exit blocks in VPlan.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114586/new/

https://reviews.llvm.org/D114586