[llvm] ca2f538 - [CodeGen] Use range-based for loops (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sat Dec 4 08:48:20 PST 2021
Author: Kazu Hirata
Date: 2021-12-04T08:48:05-08:00
New Revision: ca2f53897a2f2a60d8cb1538d5fcf930d814e9f5
URL: https://github.com/llvm/llvm-project/commit/ca2f53897a2f2a60d8cb1538d5fcf930d814e9f5
DIFF: https://github.com/llvm/llvm-project/commit/ca2f53897a2f2a60d8cb1538d5fcf930d814e9f5.diff
LOG: [CodeGen] Use range-based for loops (NFC)
Added:
Modified:
llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
llvm/lib/CodeGen/MachineCopyPropagation.cpp
llvm/lib/CodeGen/MachineFunction.cpp
llvm/lib/CodeGen/MachinePipeliner.cpp
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/lib/CodeGen/PostRASchedulerList.cpp
llvm/lib/CodeGen/RegAllocGreedy.cpp
llvm/lib/CodeGen/RegAllocPBQP.cpp
llvm/lib/CodeGen/RegisterClassInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
index e2354c40844a9..d91c30b0f8f2a 100644
--- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
@@ -833,8 +833,7 @@ void ModuleBitcodeWriter::writeAttributeTable() {
Stream.EnterSubblock(bitc::PARAMATTR_BLOCK_ID, 3);
SmallVector<uint64_t, 64> Record;
- for (unsigned i = 0, e = Attrs.size(); i != e; ++i) {
- AttributeList AL = Attrs[i];
+ for (const AttributeList &AL : Attrs) {
for (unsigned i : AL.indexes()) {
AttributeSet AS = AL.getAttributes(i);
if (AS.hasAttributes())
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index 7c83bacd80d97..57fbe4112e476 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -847,31 +847,27 @@ void MachineCopyPropagation::BackwardCopyPropagateBlock(
LLVM_DEBUG(dbgs() << "MCP: BackwardCopyPropagateBlock " << MBB.getName()
<< "\n");
- for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
- I != E;) {
- MachineInstr *MI = &*I;
- ++I;
-
+ for (MachineInstr &MI : llvm::make_early_inc_range(llvm::reverse(MBB))) {
// Ignore non-trivial COPYs.
- if (MI->isCopy() && MI->getNumOperands() == 2 &&
- !TRI->regsOverlap(MI->getOperand(0).getReg(),
- MI->getOperand(1).getReg())) {
+ if (MI.isCopy() && MI.getNumOperands() == 2 &&
+ !TRI->regsOverlap(MI.getOperand(0).getReg(),
+ MI.getOperand(1).getReg())) {
- MCRegister Def = MI->getOperand(0).getReg().asMCReg();
- MCRegister Src = MI->getOperand(1).getReg().asMCReg();
+ MCRegister Def = MI.getOperand(0).getReg().asMCReg();
+ MCRegister Src = MI.getOperand(1).getReg().asMCReg();
// Unlike forward cp, we don't invoke propagateDefs here,
// just let forward cp do COPY-to-COPY propagation.
- if (isBackwardPropagatableCopy(*MI, *MRI)) {
+ if (isBackwardPropagatableCopy(MI, *MRI)) {
Tracker.invalidateRegister(Src, *TRI);
Tracker.invalidateRegister(Def, *TRI);
- Tracker.trackCopy(MI, *TRI);
+ Tracker.trackCopy(&MI, *TRI);
continue;
}
}
// Invalidate any earlyclobber regs first.
- for (const MachineOperand &MO : MI->operands())
+ for (const MachineOperand &MO : MI.operands())
if (MO.isReg() && MO.isEarlyClobber()) {
MCRegister Reg = MO.getReg().asMCReg();
if (!Reg)
@@ -879,8 +875,8 @@ void MachineCopyPropagation::BackwardCopyPropagateBlock(
Tracker.invalidateRegister(Reg, *TRI);
}
- propagateDefs(*MI);
- for (const MachineOperand &MO : MI->operands()) {
+ propagateDefs(MI);
+ for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg())
continue;
@@ -898,7 +894,7 @@ void MachineCopyPropagation::BackwardCopyPropagateBlock(
for (MCRegUnitIterator RUI(MO.getReg().asMCReg(), TRI); RUI.isValid();
++RUI) {
if (auto *Copy = Tracker.findCopyDefViaUnit(*RUI, *TRI)) {
- CopyDbgUsers[Copy].insert(MI);
+ CopyDbgUsers[Copy].insert(&MI);
}
}
} else {
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index 310c2721c3bd1..ff3a39ecf0a63 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -1404,10 +1404,10 @@ MachineConstantPool::~MachineConstantPool() {
// A constant may be a member of both Constants and MachineCPVsSharingEntries,
// so keep track of which we've deleted to avoid double deletions.
DenseSet<MachineConstantPoolValue*> Deleted;
- for (unsigned i = 0, e = Constants.size(); i != e; ++i)
- if (Constants[i].isMachineConstantPoolEntry()) {
- Deleted.insert(Constants[i].Val.MachineCPVal);
- delete Constants[i].Val.MachineCPVal;
+ for (const MachineConstantPoolEntry &C : Constants)
+ if (C.isMachineConstantPoolEntry()) {
+ Deleted.insert(C.Val.MachineCPVal);
+ delete C.Val.MachineCPVal;
}
for (MachineConstantPoolValue *CPV : MachineCPVsSharingEntries) {
if (Deleted.count(CPV) == 0)
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 8d6459a627fa0..34f03185e3230 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -1192,14 +1192,10 @@ unsigned SwingSchedulerDAG::calculateRecMII(NodeSetType &NodeSets) {
/// but we do this to find the circuits, and then change them back.
static void swapAntiDependences(std::vector<SUnit> &SUnits) {
SmallVector<std::pair<SUnit *, SDep>, 8> DepsAdded;
- for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
- SUnit *SU = &SUnits[i];
- for (SUnit::pred_iterator IP = SU->Preds.begin(), EP = SU->Preds.end();
- IP != EP; ++IP) {
- if (IP->getKind() != SDep::Anti)
- continue;
- DepsAdded.push_back(std::make_pair(SU, *IP));
- }
+ for (SUnit &SU : SUnits) {
+ for (SDep &Pred : SU.Preds)
+ if (Pred.getKind() == SDep::Anti)
+ DepsAdded.push_back(std::make_pair(&SU, Pred));
}
for (std::pair<SUnit *, SDep> &P : DepsAdded) {
// Remove this anti dependency and add one in the reverse direction.
@@ -1471,27 +1467,23 @@ void SwingSchedulerDAG::computeNodeFunctions(NodeSetType &NodeSets) {
}
// Compute ALAP, ZeroLatencyHeight, and MOV.
- for (ScheduleDAGTopologicalSort::const_reverse_iterator I = Topo.rbegin(),
- E = Topo.rend();
- I != E; ++I) {
+ for (int I : llvm::reverse(Topo)) {
int alap = maxASAP;
int zeroLatencyHeight = 0;
- SUnit *SU = &SUnits[*I];
- for (SUnit::const_succ_iterator IS = SU->Succs.begin(),
- ES = SU->Succs.end();
- IS != ES; ++IS) {
- SUnit *succ = IS->getSUnit();
- if (IS->getLatency() == 0)
+ SUnit *SU = &SUnits[I];
+ for (const SDep &S : SU->Succs) {
+ SUnit *succ = S.getSUnit();
+ if (S.getLatency() == 0)
zeroLatencyHeight =
std::max(zeroLatencyHeight, getZeroLatencyHeight(succ) + 1);
- if (ignoreDependence(*IS, true))
+ if (ignoreDependence(S, true))
continue;
- alap = std::min(alap, (int)(getALAP(succ) - IS->getLatency() +
- getDistance(SU, succ, *IS) * MII));
+ alap = std::min(alap, (int)(getALAP(succ) - S.getLatency() +
+ getDistance(SU, succ, S) * MII));
}
- ScheduleInfo[*I].ALAP = alap;
- ScheduleInfo[*I].ZeroLatencyHeight = zeroLatencyHeight;
+ ScheduleInfo[I].ALAP = alap;
+ ScheduleInfo[I].ZeroLatencyHeight = zeroLatencyHeight;
}
// After computing the node functions, compute the summary for each node set.
@@ -1548,9 +1540,8 @@ static bool succ_L(SetVector<SUnit *> &NodeOrder,
SmallSetVector<SUnit *, 8> &Succs,
const NodeSet *S = nullptr) {
Succs.clear();
- for (SetVector<SUnit *>::iterator I = NodeOrder.begin(), E = NodeOrder.end();
- I != E; ++I) {
- for (SDep &Succ : (*I)->Succs) {
+ for (const SUnit *SU : NodeOrder) {
+ for (const SDep &Succ : SU->Succs) {
if (S && S->count(Succ.getSUnit()) == 0)
continue;
if (ignoreDependence(Succ, false))
@@ -1558,7 +1549,7 @@ static bool succ_L(SetVector<SUnit *> &NodeOrder,
if (NodeOrder.count(Succ.getSUnit()) == 0)
Succs.insert(Succ.getSUnit());
}
- for (SDep &Pred : (*I)->Preds) {
+ for (const SDep &Pred : SU->Preds) {
if (Pred.getKind() != SDep::Anti)
continue;
if (S && S->count(Pred.getSUnit()) == 0)
@@ -2899,10 +2890,8 @@ void SMSchedule::finalizeSchedule(SwingSchedulerDAG *SSD) {
// Change the registers in instruction as specified in the InstrChanges
// map. We need to use the new registers to create the correct order.
- for (int i = 0, e = SSD->SUnits.size(); i != e; ++i) {
- SUnit *SU = &SSD->SUnits[i];
- SSD->applyInstrChange(SU->getInstr(), *this);
- }
+ for (const SUnit &SU : SSD->SUnits)
+ SSD->applyInstrChange(SU.getInstr(), *this);
// Reorder the instructions in each cycle to fix and improve the
// generated code.
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 47d40f0823c8f..5f7181c656905 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -561,11 +561,10 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
MBBRegionsVector MBBRegions;
getSchedRegions(&*MBB, MBBRegions, Scheduler.doMBBSchedRegionsTopDown());
- for (MBBRegionsVector::iterator R = MBBRegions.begin();
- R != MBBRegions.end(); ++R) {
- MachineBasicBlock::iterator I = R->RegionBegin;
- MachineBasicBlock::iterator RegionEnd = R->RegionEnd;
- unsigned NumRegionInstrs = R->NumRegionInstrs;
+ for (const SchedRegion &R : MBBRegions) {
+ MachineBasicBlock::iterator I = R.RegionBegin;
+ MachineBasicBlock::iterator RegionEnd = R.RegionEnd;
+ unsigned NumRegionInstrs = R.NumRegionInstrs;
// Notify the scheduler of the region, even if we may skip scheduling
// it. Perhaps it still needs to be bundled.
diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp
index b85f00a61eac1..954396c8bf682 100644
--- a/llvm/lib/CodeGen/PostRASchedulerList.cpp
+++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp
@@ -252,8 +252,8 @@ void SchedulePostRATDList::exitRegion() {
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
/// dumpSchedule - dump the scheduled Sequence.
LLVM_DUMP_METHOD void SchedulePostRATDList::dumpSchedule() const {
- for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
- if (SUnit *SU = Sequence[i])
+ for (const SUnit *SU : Sequence) {
+ if (SU)
dumpNode(*SU);
else
dbgs() << "**** NOOP ****\n";
@@ -531,11 +531,11 @@ void SchedulePostRATDList::ListScheduleTopDown() {
ReleaseSuccessors(&EntrySU);
// Add all leaves to Available queue.
- for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
+ for (SUnit &SUnit : SUnits) {
// It is available if it has no predecessors.
- if (!SUnits[i].NumPredsLeft && !SUnits[i].isAvailable) {
- AvailableQueue.push(&SUnits[i]);
- SUnits[i].isAvailable = true;
+ if (!SUnit.NumPredsLeft && !SUnit.isAvailable) {
+ AvailableQueue.push(&SUnit);
+ SUnit.isAvailable = true;
}
}
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 50411c177007f..9eab8746982a4 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -1769,8 +1769,8 @@ void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit,
// the ActiveBlocks list with each candidate. We need to filter out
// duplicates.
BitVector Todo = SA->getThroughBlocks();
- for (unsigned c = 0; c != UsedCands.size(); ++c) {
- ArrayRef<unsigned> Blocks = GlobalCand[UsedCands[c]].ActiveBlocks;
+ for (unsigned UsedCand : UsedCands) {
+ ArrayRef<unsigned> Blocks = GlobalCand[UsedCand].ActiveBlocks;
for (unsigned Number : Blocks) {
if (!Todo.test(Number))
continue;
diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp
index b22eb080791ee..93be8f689d573 100644
--- a/llvm/lib/CodeGen/RegAllocPBQP.cpp
+++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp
@@ -623,8 +623,8 @@ void RegAllocPBQP::initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM,
// Compute an initial allowed set for the current vreg.
std::vector<MCRegister> VRegAllowed;
ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF);
- for (unsigned I = 0; I != RawPRegOrder.size(); ++I) {
- MCRegister PReg(RawPRegOrder[I]);
+ for (MCPhysReg R : RawPRegOrder) {
+ MCRegister PReg(R);
if (MRI.isReserved(PReg))
continue;
diff --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp
index 797899fb5b861..65a65b9cae958 100644
--- a/llvm/lib/CodeGen/RegisterClassInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp
@@ -109,8 +109,7 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
// FIXME: Once targets reserve registers instead of removing them from the
// allocation order, we can simply use begin/end here.
ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
- for (unsigned i = 0; i != RawOrder.size(); ++i) {
- unsigned PhysReg = RawOrder[i];
+ for (unsigned PhysReg : RawOrder) {
// Remove reserved registers from the allocation order.
if (Reserved.test(PhysReg))
continue;
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