[PATCH] D114640: [PowerPC] Handle Vector Sum Reducation

[Amy Kwan via Phabricator via llvm-commits]

amyk added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10757
+  case MVT::v16i32: {
+    if (VecInput.getOpcode() != ISD::SIGN_EXTEND &&
+        VecInput.getOpcode() != ISD::ZERO_EXTEND)
----------------
It looks like this portion:
```
    if (VecInput.getOpcode() != ISD::SIGN_EXTEND &&
        VecInput.getOpcode() != ISD::ZERO_EXTEND)
      return SDValue();

    // Check that we are extending from v16i8 to v16i32.
    if (VecInput.getOperand(0).getSimpleValueType() != MVT::v16i8)
      return SDValue();
```
is common in both cases. Does it make sense to pull this part out of the case statements so we don't duplicate it?


================
Comment at: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp:93
+  // Only expand types that are fed by zero extends or sign extends.
+  if (OperandInstr->getOpcode() != Instruction::SExt &&
+      OperandInstr->getOpcode() != Instruction::ZExt)
----------------
I think it would be good to save the opcode first, and then use it in this condition.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D114640/new/

https://reviews.llvm.org/D114640