[PATCH] D114198: [GlobalISel] Rework more/fewer elements for vectors

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic updated this revision to Diff 391611.
Petar.Avramovic added a comment.

Rebase and ping.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114198/new/

https://reviews.llvm.org/D114198

Files:
  llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
  llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
  llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
  llvm/include/llvm/CodeGen/GlobalISel/Utils.h
  llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
  llvm/lib/CodeGen/GlobalISel/Utils.cpp
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
  llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.xfail.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
  llvm/test/CodeGen/AMDGPU/ds-alignment.ll
  llvm/test/CodeGen/AMDGPU/fp-min-max-atomics.ll
  llvm/test/CodeGen/AMDGPU/lds-atomic-fmin-fmax.ll
  llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
  llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp