[llvm] 0eebe2e - AMDGPU: Sanitized functions require implicit arguments
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 2 15:19:44 PST 2021
Author: Matt Arsenault
Date: 2021-12-02T17:55:43-05:00
New Revision: 0eebe2e36c69654fe93a54f02ce06552527b0dfa
URL: https://github.com/llvm/llvm-project/commit/0eebe2e36c69654fe93a54f02ce06552527b0dfa
DIFF: https://github.com/llvm/llvm-project/commit/0eebe2e36c69654fe93a54f02ce06552527b0dfa.diff
LOG: AMDGPU: Sanitized functions require implicit arguments
Do not infer no-amdgpu-implicitarg-ptr for sanitized functions. If a
function is explicitly marked amdgpu-no-implicitarg-ptr and
sanitize_address, infer that it is required.
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
index f0aadab3302ff..ce702c3297ba8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
@@ -112,6 +112,17 @@ static bool isDSAddress(const Constant *C) {
return AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS;
}
+/// Returns true if the function requires the implicit argument be passed
+/// regardless of the function contents.
+static bool funcRequiresImplicitArgPtr(const Function &F) {
+ // Sanitizers require the hostcall buffer passed in the implicit arguments.
+ return F.hasFnAttribute(Attribute::SanitizeAddress) ||
+ F.hasFnAttribute(Attribute::SanitizeThread) ||
+ F.hasFnAttribute(Attribute::SanitizeMemory) ||
+ F.hasFnAttribute(Attribute::SanitizeHWAddress) ||
+ F.hasFnAttribute(Attribute::SanitizeMemTag);
+}
+
namespace {
class AMDGPUInformationCache : public InformationCache {
public:
@@ -339,7 +350,17 @@ struct AAAMDAttributesFunction : public AAAMDAttributes {
void initialize(Attributor &A) override {
Function *F = getAssociatedFunction();
+
+ // If the function requires the implicit arg pointer due to sanitizers,
+ // assume it's needed even if explicitly marked as not requiring it.
+ const bool NeedsImplicit = funcRequiresImplicitArgPtr(*F);
+ if (NeedsImplicit)
+ removeAssumedBits(IMPLICIT_ARG_PTR);
+
for (auto Attr : ImplicitAttrs) {
+ if (NeedsImplicit && Attr.first == IMPLICIT_ARG_PTR)
+ continue;
+
if (F->hasFnAttribute(Attr.second))
addKnownBits(Attr.first);
}
diff --git a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
index d6e87b37cf52e..21408e293958d 100644
--- a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
@@ -688,7 +688,7 @@ define void @func_call_asm() #3 {
;
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_call_asm
; ATTRIBUTOR_HSA-SAME: () #[[ATTR16]] {
-; ATTRIBUTOR_HSA-NEXT: call void asm sideeffect "", ""() #[[ATTR17:[0-9]+]]
+; ATTRIBUTOR_HSA-NEXT: call void asm sideeffect "", ""() #[[ATTR20:[0-9]+]]
; ATTRIBUTOR_HSA-NEXT: ret void
;
call void asm sideeffect "", ""() #3
@@ -837,10 +837,95 @@ define float @func_other_intrinsic_call(float %arg) #3 {
ret float %fadd
}
+; Implicit arguments need to be enabled for sanitizers
+define amdgpu_kernel void @kern_sanitize_address() #4 {
+; AKF_HSA-LABEL: define {{[^@]+}}@kern_sanitize_address
+; AKF_HSA-SAME: () #[[ATTR5:[0-9]+]] {
+; AKF_HSA-NEXT: store volatile i32 0, i32 addrspace(1)* null, align 4
+; AKF_HSA-NEXT: ret void
+;
+; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@kern_sanitize_address
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR17:[0-9]+]] {
+; ATTRIBUTOR_HSA-NEXT: store volatile i32 0, i32 addrspace(1)* null, align 4
+; ATTRIBUTOR_HSA-NEXT: ret void
+;
+ store volatile i32 0, i32 addrspace(1)* null
+ ret void
+}
+
+; Implicit arguments need to be enabled for sanitizers
+define void @func_sanitize_address() #4 {
+; AKF_HSA-LABEL: define {{[^@]+}}@func_sanitize_address
+; AKF_HSA-SAME: () #[[ATTR5]] {
+; AKF_HSA-NEXT: store volatile i32 0, i32 addrspace(1)* null, align 4
+; AKF_HSA-NEXT: ret void
+;
+; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_sanitize_address
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR17]] {
+; ATTRIBUTOR_HSA-NEXT: store volatile i32 0, i32 addrspace(1)* null, align 4
+; ATTRIBUTOR_HSA-NEXT: ret void
+;
+ store volatile i32 0, i32 addrspace(1)* null
+ ret void
+}
+
+; Implicit arguments need to be enabled for sanitizers
+define void @func_indirect_sanitize_address() #3 {
+; AKF_HSA-LABEL: define {{[^@]+}}@func_indirect_sanitize_address
+; AKF_HSA-SAME: () #[[ATTR3]] {
+; AKF_HSA-NEXT: call void @func_sanitize_address()
+; AKF_HSA-NEXT: ret void
+;
+; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@func_indirect_sanitize_address
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR18:[0-9]+]] {
+; ATTRIBUTOR_HSA-NEXT: call void @func_sanitize_address()
+; ATTRIBUTOR_HSA-NEXT: ret void
+;
+ call void @func_sanitize_address()
+ ret void
+}
+
+; Implicit arguments need to be enabled for sanitizers
+define amdgpu_kernel void @kern_indirect_sanitize_address() #3 {
+; AKF_HSA-LABEL: define {{[^@]+}}@kern_indirect_sanitize_address
+; AKF_HSA-SAME: () #[[ATTR4]] {
+; AKF_HSA-NEXT: call void @func_sanitize_address()
+; AKF_HSA-NEXT: ret void
+;
+; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@kern_indirect_sanitize_address
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR18]] {
+; ATTRIBUTOR_HSA-NEXT: call void @func_sanitize_address()
+; ATTRIBUTOR_HSA-NEXT: ret void
+;
+ call void @func_sanitize_address()
+ ret void
+}
+
+; Marked with amdgpu-no-implicitarg-ptr, and
+; sanitize_address. sanitize_address wins and requires the pointer.
+declare void @extern_func_sanitize_address() #5
+
+define amdgpu_kernel void @kern_decl_sanitize_address() #3 {
+; AKF_HSA-LABEL: define {{[^@]+}}@kern_decl_sanitize_address
+; AKF_HSA-SAME: () #[[ATTR4]] {
+; AKF_HSA-NEXT: call void @extern_func_sanitize_address()
+; AKF_HSA-NEXT: ret void
+;
+; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@kern_decl_sanitize_address
+; ATTRIBUTOR_HSA-SAME: () #[[ATTR15]] {
+; ATTRIBUTOR_HSA-NEXT: call void @extern_func_sanitize_address()
+; ATTRIBUTOR_HSA-NEXT: ret void
+;
+ call void @extern_func_sanitize_address()
+ ret void
+}
+
attributes #0 = { nounwind readnone speculatable }
attributes #1 = { nounwind "target-cpu"="fiji" }
attributes #2 = { nounwind "target-cpu"="gfx900" }
attributes #3 = { nounwind }
+attributes #4 = { nounwind sanitize_address }
+attributes #5 = { nounwind sanitize_address "amdgpu-no-implicitarg-ptr" }
;.
; AKF_HSA: attributes #[[ATTR0:[0-9]+]] = { nounwind readnone speculatable willreturn }
@@ -848,6 +933,8 @@ attributes #3 = { nounwind }
; AKF_HSA: attributes #[[ATTR2]] = { nounwind "target-cpu"="gfx900" }
; AKF_HSA: attributes #[[ATTR3]] = { nounwind }
; AKF_HSA: attributes #[[ATTR4]] = { nounwind "amdgpu-calls" }
+; AKF_HSA: attributes #[[ATTR5]] = { nounwind sanitize_address }
+; AKF_HSA: attributes #[[ATTR6:[0-9]+]] = { nounwind sanitize_address "amdgpu-no-implicitarg-ptr" }
;.
; ATTRIBUTOR_HSA: attributes #[[ATTR0:[0-9]+]] = { nounwind readnone speculatable willreturn }
; ATTRIBUTOR_HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" }
@@ -866,5 +953,8 @@ attributes #3 = { nounwind }
; ATTRIBUTOR_HSA: attributes #[[ATTR14]] = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" }
; ATTRIBUTOR_HSA: attributes #[[ATTR15]] = { nounwind "uniform-work-group-size"="false" }
; ATTRIBUTOR_HSA: attributes #[[ATTR16]] = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
-; ATTRIBUTOR_HSA: attributes #[[ATTR17]] = { nounwind }
+; ATTRIBUTOR_HSA: attributes #[[ATTR17]] = { nounwind sanitize_address "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR18]] = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR19:[0-9]+]] = { nounwind sanitize_address "amdgpu-no-implicitarg-ptr" "uniform-work-group-size"="false" }
+; ATTRIBUTOR_HSA: attributes #[[ATTR20]] = { nounwind }
;.
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