[llvm] c6fa4c4 - [AArch64] Fix unused variable warning with NDEBUG, NFC

[Reid Kleckner via llvm-commits]

Author: Reid Kleckner
Date: 2021-12-01T09:28:22-08:00
New Revision: c6fa4c481a3f41ea5730f6661fff3f2a6cda6f30

URL: https://github.com/llvm/llvm-project/commit/c6fa4c481a3f41ea5730f6661fff3f2a6cda6f30
DIFF: https://github.com/llvm/llvm-project/commit/c6fa4c481a3f41ea5730f6661fff3f2a6cda6f30.diff

LOG: [AArch64] Fix unused variable warning with NDEBUG, NFC

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 563f2b7a07351..3d9a626d3ac38 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -2934,8 +2934,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
       if (!SrcTy.isVector() && SrcTy.getSizeInBits() == 32 &&
           ShiftTy.getSizeInBits() == 64) {
         assert(!ShiftTy.isVector() && "unexpected vector shift ty");
-        auto *AmtMI = MRI.getVRegDef(ShiftReg);
-        assert(AmtMI && "could not find a vreg definition for shift amount");
+        assert(MRI.getVRegDef(ShiftReg) &&
+               "could not find a vreg definition for shift amount");
         // Insert a subregister copy to implement a 64->32 trunc
         auto Trunc = MIB.buildInstr(TargetOpcode::COPY, {SrcTy}, {})
                          .addReg(ShiftReg, 0, AArch64::sub_32);