[PATCH] D114652: [AMDGPU] Treat call clobbered return address registers s[30:31] as callee saved

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:630-633
+  // The return address register is call clobbered and the CFI needs to track
+  // its location. Hence it is handled specially.
+  if (!MFI->isEntryFunction())
+    reserveRegisterTuples(Reserved, getReturnAddressReg(MF));
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arsenm wrote:
> RamNalamothu wrote:
> > arsenm wrote:
> > > I don't think it's necessary to reserve this
> > But otherwise the register allocation thinks it is available for allocation as `s[30:31]` are scratch registers at the moment and its usage with return instruction is hidden with using SI_RETURN through the register allocation and we don't emit Live-ins anymore.
> > 
> > And we will have to reserve it here even after these registers actually get picked from **CSR range** because we want to emit save/restore exclusively so that the unwind info machinery knows it and can generate CFI as needed for return address. That's the reason why all of this got started right.
> I think something special happens with the return address we are ignoring, but I haven't followed it all the way through.
> 
> AArch64 passes LR to the TargetRegisterInfo constructor, where we're passing the dummy PC_REG. If you replace that with the real return address, does that help?
Even if not, AArch64 does not reserve the return address


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https://reviews.llvm.org/D114652