[llvm] 0eb1efb - [DAGCombiner] When combining REM ensure optimized div nodes are unique

[Bradley Smith via llvm-commits]

Author: Bradley Smith
Date: 2021-12-01T11:24:26Z
New Revision: 0eb1efb92c3078789242d89a1e914d968cf1297f

URL: https://github.com/llvm/llvm-project/commit/0eb1efb92c3078789242d89a1e914d968cf1297f
DIFF: https://github.com/llvm/llvm-project/commit/0eb1efb92c3078789242d89a1e914d968cf1297f.diff

LOG: [DAGCombiner] When combining REM ensure optimized div nodes are unique

The REM DAG combine uses the visitDivLike functions to try and get an
optimized DIV node to provide better codegen, however in some cases this
visitDivLike call ends up in the BuildSDIVPow2 target hook, which in
turn sometimes will return the same node passed in to indicate not to
change it. The REM DAG combine does not anticipate this and creates a
cycle in the DAG because of it.

Fix this by ensuring any such optimized div node returned is distinct
from the node being combined.

Differential Revision: https://reviews.llvm.org/D114716

Added: 
    llvm/test/CodeGen/AArch64/sve-srem-combine-loop.ll

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 194a6d6d5a68a..9048c24a7af88 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4436,7 +4436,7 @@ SDValue DAGCombiner::visitREM(SDNode *N) {
   if (DAG.isKnownNeverZero(N1) && !TLI.isIntDivCheap(VT, Attr)) {
     SDValue OptimizedDiv =
         isSigned ? visitSDIVLike(N0, N1, N) : visitUDIVLike(N0, N1, N);
-    if (OptimizedDiv.getNode()) {
+    if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != N) {
       // If the equivalent Div node also exists, update its users.
       unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
       if (SDNode *DivNode = DAG.getNodeIfExists(DivOpcode, N->getVTList(),

diff  --git a/llvm/test/CodeGen/AArch64/sve-srem-combine-loop.ll b/llvm/test/CodeGen/AArch64/sve-srem-combine-loop.ll
new file mode 100644
index 0000000000000..102abfe07bc9e
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-srem-combine-loop.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+define <vscale x 4 x i32> @srem_combine_loop(<vscale x 4 x i32> %a) #0 {
+; CHECK-LABEL: srem_combine_loop:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z1.d, z0.d
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    asrd z1.s, p0/m, z1.s, #1
+; CHECK-NEXT:    mov z2.s, #2 // =0x2
+; CHECK-NEXT:    mls z0.s, p0/m, z1.s, z2.s
+; CHECK-NEXT:    ret
+  %rem = srem <vscale x 4 x i32> %a, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 2, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
+  ret <vscale x 4 x i32> %rem
+}
+
+attributes #0 = { "target-features"="+sve" }