[PATCH] D114768: [ADT] Remove 0-width Asserts in APInt.getZExtValue

[Schuyler Eldridge via Phabricator via llvm-commits]

seldridge updated this revision to Diff 390803.
seldridge retitled this revision from "[ADT][Support] Remove zero-width assertions" to "[ADT] Remove 0-width Asserts in APInt.getZExtValue".
seldridge edited the summary of this revision.
seldridge added a comment.

Update commit message/diff summary to reflect reduced scope.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114768/new/

https://reviews.llvm.org/D114768

Files:
  llvm/include/llvm/ADT/APInt.h
  llvm/unittests/ADT/APIntTest.cpp


Index: llvm/unittests/ADT/APIntTest.cpp
===================================================================
--- llvm/unittests/ADT/APIntTest.cpp
+++ llvm/unittests/ADT/APIntTest.cpp
@@ -3054,6 +3054,9 @@
   EXPECT_EQ(0U, APInt(4, 3).trunc(0).getBitWidth());
   EXPECT_TRUE(ZW.isAllOnes());
 
+  // Sign extension.
+  EXPECT_EQ(0U, ZW.getZExtValue());
+
   SmallString<42> STR;
   ZW.toStringUnsigned(STR);
   EXPECT_EQ("0", STR);
Index: llvm/include/llvm/ADT/APInt.h
===================================================================
--- llvm/include/llvm/ADT/APInt.h
+++ llvm/include/llvm/ADT/APInt.h
@@ -1458,10 +1458,8 @@
   /// uint64_t. The bitwidth must be <= 64 or the value must fit within a
   /// uint64_t. Otherwise an assertion will result.
   uint64_t getZExtValue() const {
-    if (isSingleWord()) {
-      assert(BitWidth && "zero width values not allowed");
+    if (isSingleWord())
       return U.VAL;
-    }
     assert(getActiveBits() <= 64 && "Too many bits for uint64_t");
     return U.pVal[0];
   }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D114768.390803.patch
Type: text/x-patch
Size: 1025 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20211130/514ed658/attachment.bin>