[PATCH] D114811: [ADT] Allow zero-width zext

[Schuyler Eldridge via Phabricator via llvm-commits]

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Remove assertion that disallows zero-extending a zero-width APInt.  This
check is too restrictive and makes it difficult to use APInt to model
zero-width things, e.g., zero-width wires in the CIRCT project.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge at sifive.com>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D114811

Files:
  llvm/include/llvm/ADT/APInt.h


Index: llvm/include/llvm/ADT/APInt.h
===================================================================
--- llvm/include/llvm/ADT/APInt.h
+++ llvm/include/llvm/ADT/APInt.h
@@ -1458,10 +1458,8 @@
   /// uint64_t. The bitwidth must be <= 64 or the value must fit within a
   /// uint64_t. Otherwise an assertion will result.
   uint64_t getZExtValue() const {
-    if (isSingleWord()) {
-      assert(BitWidth && "zero width values not allowed");
+    if (isSingleWord())
       return U.VAL;
-    }
     assert(getActiveBits() <= 64 && "Too many bits for uint64_t");
     return U.pVal[0];
   }


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