[llvm] c0b33a6 - Typo fix

[Hans Wennborg via llvm-commits]

Author: Hans Wennborg
Date: 2021-11-30T19:26:59+01:00
New Revision: c0b33a65f21c780a1a89ea7e8caa43871b2fd29c

URL: https://github.com/llvm/llvm-project/commit/c0b33a65f21c780a1a89ea7e8caa43871b2fd29c
DIFF: https://github.com/llvm/llvm-project/commit/c0b33a65f21c780a1a89ea7e8caa43871b2fd29c.diff

LOG: Typo fix

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c42584aa763f9..c45060aba8b02 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -45680,7 +45680,7 @@ static SDValue combineCompareEqual(SDNode *N, SelectionDAG &DAG,
           if (is64BitFP && !Subtarget.is64Bit()) {
             // On a 32-bit target, we cannot bitcast the 64-bit float to a
             // 64-bit integer, since that's not a legal type. Since
-            // OnesOrZeroesF is all ones of all zeroes, we don't need all the
+            // OnesOrZeroesF is all ones or all zeroes, we don't need all the
             // bits, but can do this little dance to extract the lowest 32 bits
             // and work with those going forward.
             SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,