[PATCH] D114700: AMDGPU/GlobalISel: Fix constant bus restriction errors for med3

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir:14
 
-    ; CHECK-LABEL: name: test_min_max_ValK0_K1_i32
-    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
-    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12
-    ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
-    ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[C]], [[C1]]
-    ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
-    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
-    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
+    ; GFX9-LABEL: name: test_min_max_ValK0_K1_i32
+    ; GFX9: liveins: $vgpr0, $sgpr30_sgpr31
----------------
What is the difference between GFX9 and GFX10 here? Can they use a common prefix?


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  https://reviews.llvm.org/D114700/new/

https://reviews.llvm.org/D114700