[PATCH] D114581: [RISCV] Fix a crash in decoding LMUL in VTYPE

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D114581#3159867 <https://reviews.llvm.org/D114581#3159867>, @jrtc27 wrote:

> In D114581#3159747 <https://reviews.llvm.org/D114581#3159747>, @craig.topper wrote:
>
>> In D114581#3159433 <https://reviews.llvm.org/D114581#3159433>, @jrtc27 wrote:
>>
>>> Looking at the vector spec, what about SEW? All of 100-111 are currently reserved. And why's vtypei 11 bits; isn't it 9 in the spec (12 I could understand if zero-extending to fill the I-type value, but 11 is odd)? Maybe I'm missing something, just glancing through.
>>
>> `vsetvli` uses 11 bits zimm[10:0] (bits 30:20 of the instruction), vsetivli uses 10 bits zimm[9:0] (bits 29:20 of the instruction). `vsetvli` is the older instruction and uses more bits. I assume that's where the 11 came from.
>
> Ok. What do the other bit(s) mean? Are they ignored or treated as invalid (until such time as they are given meaning)? I can't obviously see a specification for how the bits are actually encoded in `zimm[10:0]`, just "The new vtype setting is encoded in the immediate