[PATCH] D114581: [RISCV] Fix a crash in decoding LMUL in VTYPE

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D114581#3159433 <https://reviews.llvm.org/D114581#3159433>, @jrtc27 wrote:

> Looking at the vector spec, what about SEW? All of 100-111 are currently reserved. And why's vtypei 11 bits; isn't it 9 in the spec (12 I could understand if zero-extending to fill the I-type value, but 11 is odd)? Maybe I'm missing something, just glancing through.

`vsetvli` uses 11 bits zimm[10:0] (bits 30:20 of the instruction), vsetivli uses 10 bits zimm[9:0] (bits 29:20 of the instruction). `vsetvli` is the older instruction and uses more bits. I assume that's where the 11 came from.



================
Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:280-281
+                                 const void *Decoder) {
+  // The encoding LMUL=4 is reserved and could be used for something
+  // completely different in the future.
+  if ((Imm & 7) == 4)
----------------
jrtc27 wrote:
> I'd just stop at "is reserved", the latter part of the sentence applies to any reserved encoding so doesn't need special mention, just that it's LMUL=4 (technically vlmul[2:0]; LMUL is the name for the decoded value, vlmul is the actual encoded thing) we're checking for here.
Agree this should mention vlmul not LMUL. I should have caught that.


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