[PATCH] D112811: [ARM] implement LOAD_STACK_GUARD for remaining targets

[Hans Wennborg via Phabricator via llvm-commits]

hans added a comment.

In D112811#3144510 <https://reviews.llvm.org/D112811#3144510>, @hans wrote:

> We bisected some Chromium test failures on Android, which points to this change (https://crbug.com/1270361). We'll investigate further, just wanted to give a heads up.

What we're hitting seems to be that the LOAD_STACK_GUARD pseudo-instruction can be register allocated to one of the high Thumb registers (in our case r12), but gets expanded using the tLDRLIT_ga_pcrel pseudo, which cannot take a high Thumb register as output.

It tries anyway, and generates the following textual asm:

  ldr     r12, .LCPI0_0 

but what it actually encodes is this:

  4: 11 4c         ldr     r4, [pc, #68]

(Note the different register.)

I've uploaded a reproducer here: https://bugs.chromium.org/p/chromium/issues/detail?id=1270361#c30

I'm not sure what the best fix is. Maybe the register class for LOAD_STACK_GUARD could be restricted, or maybe tLDRLIT_ga_pcrel could be made to work with the high registers.

In any case, unless you can think of an immediate fix, I'd like to revert this in the meantime.


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