[PATCH] D114700: AMDGPU/GlobalISel: Fix constant bus restriction errors for med3

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp:136
   B.setInstrAndDebugLoc(MI);
-  B.buildInstr(MatchInfo.Opc, {MI.getOperand(0)},
-               {MatchInfo.Val0, MatchInfo.Val1, MatchInfo.Val2}, MI.getFlags());
+  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
+  unsigned ConstantBusLimit = ST.getConstantBusLimit(MatchInfo.Opc);
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The subtarget should probably be cached in the combiner helper


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Comment at: llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp:137
+  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
+  unsigned ConstantBusLimit = ST.getConstantBusLimit(MatchInfo.Opc);
+  SmallVector<Register, 3> Regs(
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My intention was globalisel should not need to think about the constant bus restriction at all because it will be quickly become unmanageable. All code would need to be exactly aware of how the instructions will be selected, which is impossible.

All VALU instructions should use all VGPR (or VCC) mappings


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Comment at: llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp:148
+    }
+    if (NumSgprUsed >= ConstantBusLimit) {
+      auto CopyToVgpr = B.buildCopy(MRI.getType(Regs[i]), Regs[i]);
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Should not consider individual mappings, everything just needs to be VGPR


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Comment at: llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp:149-152
+      auto CopyToVgpr = B.buildCopy(MRI.getType(Regs[i]), Regs[i]);
+      MRI.setRegBank(CopyToVgpr.getReg(0),
+                     RBI.getRegBank(AMDGPU::VGPRRegBankID));
+      SrcOps.push_back(CopyToVgpr.getReg(0));
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Probably should have a constrain or copy to VGPR helper


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  https://reviews.llvm.org/D114700/new/

https://reviews.llvm.org/D114700