[PATCH] D108115: [DAG][sve] Lowering for VLS masked truncating stores

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9843
+  // truncating store.  We can do this even if this is already a truncstore.
+  if ((Value.getOpcode() == ISD::FP_ROUND ||
+       Value.getOpcode() == ISD::TRUNCATE) &&
----------------
This will fail once D114580 lands because that patch breaks the symmetry between truncating stores and masked truncating stores.  If we can drop the `ISD::FP_ROUND` part of the combine then great otherwise we either need to add support for floating point to this patch or wait for D112536.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:18163
+    Mask = DAG.getNode(
+        ISD::ZERO_EXTEND, DL,
+        VT.changeVectorElementType(ContainerVT.getVectorElementType()), Mask);
----------------
For consistency this should be `ISD::SIGN_EXTEND` given on AArch64 fixed length masks are either zero or all ones.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108115/new/

https://reviews.llvm.org/D108115