[llvm] 562356d - [Target] Use range-based for loops (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 26 08:23:11 PST 2021
Author: Kazu Hirata
Date: 2021-11-26T08:23:01-08:00
New Revision: 562356d6e3b5aaceddb4fff34af5fbdcb6748570
URL: https://github.com/llvm/llvm-project/commit/562356d6e3b5aaceddb4fff34af5fbdcb6748570
DIFF: https://github.com/llvm/llvm-project/commit/562356d6e3b5aaceddb4fff34af5fbdcb6748570.diff
LOG: [Target] Use range-based for loops (NFC)
Added:
Modified:
llvm/lib/Target/ARC/ARCMCInstLower.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
llvm/lib/Target/BPF/BPFMCInstLower.cpp
llvm/lib/Target/Hexagon/BitTracker.cpp
llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARC/ARCMCInstLower.cpp b/llvm/lib/Target/ARC/ARCMCInstLower.cpp
index 62462b77eccf..50ba9fe75232 100644
--- a/llvm/lib/Target/ARC/ARCMCInstLower.cpp
+++ b/llvm/lib/Target/ARC/ARCMCInstLower.cpp
@@ -104,8 +104,7 @@ MCOperand ARCMCInstLower::LowerOperand(const MachineOperand &MO,
void ARCMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (const MachineOperand &MO : MI->operands()) {
MCOperand MCOp = LowerOperand(MO);
if (MCOp.isValid())
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 2d981be4cfc1..918308318bee 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -310,8 +310,7 @@ ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
// Transfer LiveVariables states, kill / dead info.
if (LV) {
- for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI.getOperand(i);
+ for (const MachineOperand &MO : MI.operands()) {
if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
Register Reg = MO.getReg();
@@ -634,8 +633,7 @@ bool ARMBaseInstrInfo::ClobbersPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred,
bool SkipDead) const {
bool Found = false;
- for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI.getOperand(i);
+ for (const MachineOperand &MO : MI.operands()) {
bool ClobbersCPSR = MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR);
bool IsCPSR = MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR;
if (ClobbersCPSR || IsCPSR) {
@@ -732,8 +730,7 @@ bool ARMBaseInstrInfo::isPredicable(const MachineInstr &MI) const {
namespace llvm {
template <> bool IsCPSRDead<MachineInstr>(const MachineInstr *MI) {
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg() || MO.isUndef() || MO.isUse())
continue;
if (MO.getReg() != ARM::CPSR)
@@ -2312,8 +2309,7 @@ ARMBaseInstrInfo::canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,
return nullptr;
// Check if MI has any non-dead defs or physreg uses. This also detects
// predicated instructions which will be reading CPSR.
- for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 1)) {
// Reject frame index operands, PEI can't handle the predicated pseudos.
if (MO.isFI() || MO.isCPI() || MO.isJTI())
return nullptr;
@@ -4857,11 +4853,10 @@ bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI,
if (MI.getOpcode() == ARM::tPUSH ||
MI.getOpcode() == ARM::tPOP ||
MI.getOpcode() == ARM::tPOP_RET) {
- for (int i = 2, e = MI.getNumOperands(); i < e; ++i) {
- if (MI.getOperand(i).isImplicit() ||
- !MI.getOperand(i).isReg())
+ for (const MachineOperand &MO : llvm::drop_begin(MI.operands(), 2)) {
+ if (MO.isImplicit() || !MO.isReg())
continue;
- Register Reg = MI.getOperand(i).getReg();
+ Register Reg = MO.getReg();
if (Reg < ARM::R0 || Reg > ARM::R7) {
if (!(MI.getOpcode() == ARM::tPUSH && Reg == ARM::LR) &&
!(MI.getOpcode() == ARM::tPOP_RET && Reg == ARM::PC)) {
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index a8f09969e948..900be964e533 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -125,9 +125,8 @@ void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
MachineInstrBuilder &UseMI,
MachineInstrBuilder &DefMI) {
const MCInstrDesc &Desc = OldMI.getDesc();
- for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
- i != e; ++i) {
- const MachineOperand &MO = OldMI.getOperand(i);
+ for (const MachineOperand &MO :
+ llvm::drop_begin(OldMI.operands(), Desc.getNumOperands())) {
assert(MO.isReg() && MO.getReg());
if (MO.isUse())
UseMI.add(MO);
@@ -2252,8 +2251,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
.add(predOps(ARMCC::AL))
.addReg(JumpReg, RegState::Kill);
- for (int I = 1, E = MI.getNumOperands(); I != E; ++I)
- NewCall->addOperand(MI.getOperand(I));
+ for (const MachineOperand &MO : llvm::drop_begin(MI.operands()))
+ NewCall->addOperand(MO);
if (MI.isCandidateForCallSiteEntry())
MI.getMF()->moveCallSiteInfo(&MI, NewCall.getInstr());
@@ -3065,7 +3064,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL));
}
MIB.cloneMemRefs(MI);
- for (unsigned i = 1; i < MI.getNumOperands(); ++i) MIB.add(MI.getOperand(i));
+ for (const MachineOperand &MO : llvm::drop_begin(MI.operands()))
+ MIB.add(MO);
MI.eraseFromParent();
return true;
}
@@ -3080,8 +3080,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
Opcode == ARM::LOADDUAL ? RegState::Define : 0)
.addReg(TRI->getSubReg(PairReg, ARM::gsub_1),
Opcode == ARM::LOADDUAL ? RegState::Define : 0);
- for (unsigned i = 1; i < MI.getNumOperands(); i++)
- MIB.add(MI.getOperand(i));
+ for (const MachineOperand &MO : llvm::drop_begin(MI.operands()))
+ MIB.add(MO);
MIB.add(predOps(ARMCC::AL));
MIB.cloneMemRefs(MI);
MI.eraseFromParent();
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index d87ef2babf16..1a9f3a59aa58 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -11771,8 +11771,8 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
}
MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
- for (unsigned i = 0; i < MI.getNumOperands(); ++i)
- MIB.add(MI.getOperand(i));
+ for (const MachineOperand &MO : MI.operands())
+ MIB.add(MO);
MI.eraseFromParent();
return BB;
}
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 96f80cd38ecc..8568aa4c1a50 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -1298,8 +1298,8 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineInstr *MI) {
// Can't use an updating ld/st if the base register is also a dest
// register. e.g. ldmdb r0!, {r0, r1, r2}. The behavior is undefined.
- for (unsigned i = 2, e = MI->getNumOperands(); i != e; ++i)
- if (MI->getOperand(i).getReg() == Base)
+ for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
+ if (MO.getReg() == Base)
return false;
int Bytes = getLSMultipleTransferSize(MI);
@@ -1350,8 +1350,8 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineInstr *MI) {
.addImm(Pred).addReg(PredReg);
// Transfer the rest of operands.
- for (unsigned OpNum = 3, e = MI->getNumOperands(); OpNum != e; ++OpNum)
- MIB.add(MI->getOperand(OpNum));
+ for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 3))
+ MIB.add(MO);
// Transfer memoperands.
MIB.setMemRefs(MI->memoperands());
diff --git a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
index 132516694f4e..1164b6ebbac3 100644
--- a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
+++ b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
@@ -502,8 +502,8 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
// For the non-writeback version (this one), the base register must be
// one of the registers being loaded.
bool isOK = false;
- for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
- if (MI->getOperand(i).getReg() == BaseReg) {
+ for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 3)) {
+ if (MO.getReg() == BaseReg) {
isOK = true;
break;
}
@@ -527,8 +527,8 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
// numbered register (i.e. it's in operand 4 onwards) then with writeback
// the stored value is unknown, so we can't convert to tSTMIA_UPD.
Register BaseReg = MI->getOperand(0).getReg();
- for (unsigned i = 4; i < MI->getNumOperands(); ++i)
- if (MI->getOperand(i).getReg() == BaseReg)
+ for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 4))
+ if (MO.getReg() == BaseReg)
return false;
break;
@@ -611,8 +611,8 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
}
// Transfer the rest of operands.
- for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
- MIB.add(MI->getOperand(OpNum));
+ for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), OpNum))
+ MIB.add(MO);
// Transfer memoperands.
MIB.setMemRefs(MI->memoperands());
diff --git a/llvm/lib/Target/BPF/BPFMCInstLower.cpp b/llvm/lib/Target/BPF/BPFMCInstLower.cpp
index 846798a63cb7..2ce9c386f24c 100644
--- a/llvm/lib/Target/BPF/BPFMCInstLower.cpp
+++ b/llvm/lib/Target/BPF/BPFMCInstLower.cpp
@@ -47,9 +47,7 @@ MCOperand BPFMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
void BPFMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
-
+ for (const MachineOperand &MO : MI->operands()) {
MCOperand MCOp;
switch (MO.getType()) {
default:
diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp
index 0f6c10a6256c..685bafd785df 100644
--- a/llvm/lib/Target/Hexagon/BitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/BitTracker.cpp
@@ -850,8 +850,7 @@ void BT::visitNonBranch(const MachineInstr &MI) {
bool Eval = ME.evaluate(MI, Map, ResMap);
if (Trace && Eval) {
- for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
- const MachineOperand &MO = MI.getOperand(i);
+ for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.isUse())
continue;
RegisterRef RU(MO);
diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
index 0ad06934898b..46c1fbc6eeb2 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
@@ -602,8 +602,7 @@ void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO) const {
continue;
for (const MachineInstr &MI : B) {
- for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
- const MachineOperand &MO = MI.getOperand(i);
+ for (const MachineOperand &MO : MI.operands()) {
if (MO.isReg() && MO.isDef()) {
Register R = MO.getReg();
assert(MO.getSubReg() == 0 && "Unexpected subregister in definition");
@@ -719,8 +718,7 @@ bool HexagonGenInsert::findNonSelfReference(unsigned VR) const {
void HexagonGenInsert::getInstrDefs(const MachineInstr *MI,
RegisterSet &Defs) const {
- for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
Register R = MO.getReg();
@@ -732,8 +730,7 @@ void HexagonGenInsert::getInstrDefs(const MachineInstr *MI,
void HexagonGenInsert::getInstrUses(const MachineInstr *MI,
RegisterSet &Uses) const {
- for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg() || !MO.isUse())
continue;
Register R = MO.getReg();
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index 0fe2f74babca..5d2e1b259449 100644
--- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -1032,8 +1032,7 @@ bool HexagonHardwareLoops::containsInvalidInstruction(MachineLoop *L,
bool HexagonHardwareLoops::isDead(const MachineInstr *MI,
SmallVectorImpl<MachineInstr *> &DeadPhis) const {
// Examine each operand.
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
@@ -1087,8 +1086,7 @@ void HexagonHardwareLoops::removeIfDead(MachineInstr *MI) {
// It is possible that some DBG_VALUE instructions refer to this
// instruction. Examine each def operand for such references;
// if found, mark the DBG_VALUE as undef (but don't delete it).
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
Register Reg = MO.getReg();
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