[PATCH] D114642: [AArch64][SchedModels] Handle virtual registers in FP/NEON predicates

[Pavel Kosov via Phabricator via llvm-commits]

kpdev42 created this revision.
kpdev42 added reviewers: dmgreen, andreadb, evandro, echristo.
kpdev42 added a project: LLVM.
Herald added subscribers: hiraditya, kristof.beyls.
kpdev42 requested review of this revision.

Current implementation of Check[HSDQ]Form predicates doesn’t handle virtual registers and therefore isn’t useful for pre-RA scheduling. Patch fixes this implementing two function predicates: CheckQForm for checking that instruction writes 128-bit NEON register and CheckFpOrNEON which checks that instruction writes FP register (any width). The latter supersedes Check[HSD]Form predicates which are not used individually.

OS Laboratory. Huawei Russian Research Institute. Saint-Petersburg


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D114642

Files:
  llvm/include/llvm/MC/MCInstrDesc.h
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.h
  llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
  llvm/lib/Target/AArch64/AArch64SchedPredicates.td
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
  llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir

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