[PATCH] D114542: [CodeGen][SVE] Use whilelo instruction when lowering @llvm.get.active.lane.mask

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tschuett added a comment.

In D114542#3155048 <https://reviews.llvm.org/D114542#3155048>, @SjoerdMeijer wrote:

> In D114542#3153131 <https://reviews.llvm.org/D114542#3153131>, @tschuett wrote:
>
>> In D114542#3153129 <https://reviews.llvm.org/D114542#3153129>, @SjoerdMeijer wrote:
>>
>>> In D114542#3153102 <https://reviews.llvm.org/D114542#3153102>, @david-arm wrote:
>>>
>>>> I think the main difference between SVE and MVE is that for MVE we have to set up some state before entering the loop, and perhaps the actual instruction that generates the predicate uses that state? Whereas for SVE we don't have that problem.
>>>
>>> Yep, and I would need to refresh my memory and read the reference manual, but I am almost certain that for MVE we would get wrong results if overflow occurs in the VCTP instructions.
>>
>> Could you add Metadata to the intrinsic to state the assumptions?
>
> Something along those lines would probably be possible, but defeats the purpose of the intrinsic, which is about communicating information from the middle-end to the back-end. If we need an intrinsic and also meta-data to achieve this, then we should probably revise the definition of the intrinsic. But it looks like we don't need to do that at the moment, and we are also good for SVE.

Totally up to you. Either state in langref that is does not overflow. Or have a different intrinsic. `llvm.get.active.lane.mask_without_overflow'.


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