[PATCH] D114351: [AMDGPU] Add SIMemoryLegalizer comments to clarify bit usage

[Tony Tye via Phabricator via llvm-commits]

t-tye added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp:868
+    // Set L1 cache policy to be MISS_EVICT for load instructions and
+    // MISS_LRU (write-combine) for store instructions.
+    // Note: there is no L2 cache bypass policy at the ISA level.
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I would not add "{write-combine)" as it really is not an exact match for that term.


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Comment at: llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp:1220
+    // Set L1 cache policy to be MISS_EVICT for load instructions and
+    // MISS_LRU (write-combine) for store instructions.
+    // Note: there is no L2 cache bypass policy at the ISA level.
----------------
Would eliminate "(write-combine)" as mentioned above.


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Comment at: llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp:1451
+    // Set L0 and L1 cache policy to be MISS_EVICT for load instructions
+    // and MISS_LRU (write-combine) for store instructions.
     if (Op == SIMemOp::LOAD) {
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Eliminate "(write-cobine)". Add:

  // Note that there is no L2 cache coherent bypass policy at the isa level.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114351/new/

https://reviews.llvm.org/D114351