[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Support/RISCVISAInfo.cpp:69
     {"zfh", RISCVExtensionVersion{0, 1}},
+    {"zfinx", RISCVExtensionVersion{1, 0}},
+    {"zdinx", RISCVExtensionVersion{1, 0}},
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Do we need to enforce that these can't be mixed with F, D, and Zfh?


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Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1718
+        !getSTI().hasFeature(RISCV::FeatureStdExtF) &&
+            !getSTI().hasFeature(RISCV::FeatureStdExtD) &&
+            !getSTI().hasFeature(RISCV::FeatureStdExtZfh)));
----------------
D and Zfh imply F. Is it enough to just check F?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoF.td:77
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class FPFMAS_rrr_frm<RISCVOpcode opcode, string opcodestr>
-    : RVInstR4Frm<0b00, opcode, (outs FPR32:$rd),
-                  (ins FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, frmarg:$funct3),
+class FPFMAS_rrr_frm_single<RISCVOpcode opcode, string opcodestr,
+                            RegisterOperand freg>
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Can we merge this with FPFMAD_rrr_frm_single and FPFMAH_rrr_frm_single by passing the 0b00/0b01/0b10 value from FPFMAS_rrr_frm/FPFMAD_rrr_frm/FPFMAH_rrr_frm?

This applies to most of the `_single` classes. We should share them if possible.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298