[llvm] d9af9c2 - [ARM] Fold floating point select(binop) patterns
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 24 02:22:26 PST 2021
Author: David Green
Date: 2021-11-24T10:22:20Z
New Revision: d9af9c2c5a53c9ba6aa0255240a2a40e8bea27aa
URL: https://github.com/llvm/llvm-project/commit/d9af9c2c5a53c9ba6aa0255240a2a40e8bea27aa
DIFF: https://github.com/llvm/llvm-project/commit/d9af9c2c5a53c9ba6aa0255240a2a40e8bea27aa.diff
LOG: [ARM] Fold floating point select(binop) patterns
Similar to D84091 which added extra predicated folds for integer operations
using the identity element of the operation, this adds them for floating
point operations for the form `BinOp(x, select(p, y, Identity))`. They are
folded back to predicated versions of the operator, with fadd having the
identity -0.0, fsub using the identity 0.0 and fmul using 1.0.
Differential Revision: https://reviews.llvm.org/D113574
Added:
Modified:
llvm/lib/Target/ARM/ARMInstrMVE.td
llvm/test/CodeGen/Thumb2/mve-pred-selectop3.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index 6977300372778..f53814a80e01e 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -3621,21 +3621,24 @@ class MVE_VMUL_fp<string iname, string suffix, bits<2> size, list<dag> pattern=[
let validForTailPredication = 1;
}
-multiclass MVE_VMULT_fp_m<string iname, MVEVectorVTInfo VTI,
- SDNode Op, Intrinsic PredInt> {
+multiclass MVE_VMULT_fp_m<string iname, MVEVectorVTInfo VTI, SDNode Op,
+ Intrinsic PredInt, SDPatternOperator IdentityVec> {
def "" : MVE_VMUL_fp<iname, VTI.Suffix, VTI.Size>;
defvar Inst = !cast<Instruction>(NAME);
let Predicates = [HasMVEFloat] in {
- defm : MVE_TwoOpPattern<VTI, Op, PredInt, (? ), !cast<Instruction>(NAME)>;
+ defm : MVE_TwoOpPattern<VTI, Op, PredInt, (? ), !cast<Instruction>(NAME), IdentityVec>;
}
}
-multiclass MVE_VMUL_fp_m<MVEVectorVTInfo VTI>
- : MVE_VMULT_fp_m<"vmul", VTI, fmul, int_arm_mve_mul_predicated>;
+multiclass MVE_VMUL_fp_m<MVEVectorVTInfo VTI, SDPatternOperator IdentityVec>
+ : MVE_VMULT_fp_m<"vmul", VTI, fmul, int_arm_mve_mul_predicated, IdentityVec>;
+
+def ARMimmOneF: PatLeaf<(bitconvert (v4f32 (ARMvmovFPImm (i32 112))))>; // 1.0 float
+def ARMimmOneH: PatLeaf<(bitconvert (v8i16 (ARMvmovImm (i32 2620))))>; // 1.0 half
-defm MVE_VMULf32 : MVE_VMUL_fp_m<MVE_v4f32>;
-defm MVE_VMULf16 : MVE_VMUL_fp_m<MVE_v8f16>;
+defm MVE_VMULf32 : MVE_VMUL_fp_m<MVE_v4f32, ARMimmOneF>;
+defm MVE_VMULf16 : MVE_VMUL_fp_m<MVE_v8f16, ARMimmOneH>;
class MVE_VCMLA<string suffix, bits<2> size>
: MVEFloatArithNeon<"vcmla", suffix, size{1}, (outs MQPR:$Qd),
@@ -3747,27 +3750,30 @@ defm MVE_VFMSf32 : MVE_VFMA_fp_multi<"vfms", 1, MVE_v4f32>;
defm MVE_VFMSf16 : MVE_VFMA_fp_multi<"vfms", 1, MVE_v8f16>;
multiclass MVE_VADDSUB_fp_m<string iname, bit bit_21, MVEVectorVTInfo VTI,
- SDNode Op, Intrinsic PredInt> {
+ SDNode Op, Intrinsic PredInt, SDPatternOperator IdentityVec> {
def "" : MVE_VADDSUBFMA_fp<iname, VTI.Suffix, VTI.Size, 0, 1, bit_21> {
let validForTailPredication = 1;
}
defvar Inst = !cast<Instruction>(NAME);
let Predicates = [HasMVEFloat] in {
- defm : MVE_TwoOpPattern<VTI, Op, PredInt, (? ), !cast<Instruction>(NAME)>;
+ defm : MVE_TwoOpPattern<VTI, Op, PredInt, (? ), !cast<Instruction>(NAME), IdentityVec>;
}
}
-multiclass MVE_VADD_fp_m<MVEVectorVTInfo VTI>
- : MVE_VADDSUB_fp_m<"vadd", 0, VTI, fadd, int_arm_mve_add_predicated>;
-multiclass MVE_VSUB_fp_m<MVEVectorVTInfo VTI>
- : MVE_VADDSUB_fp_m<"vsub", 1, VTI, fsub, int_arm_mve_sub_predicated>;
+multiclass MVE_VADD_fp_m<MVEVectorVTInfo VTI, SDPatternOperator IdentityVec>
+ : MVE_VADDSUB_fp_m<"vadd", 0, VTI, fadd, int_arm_mve_add_predicated, IdentityVec>;
+multiclass MVE_VSUB_fp_m<MVEVectorVTInfo VTI, SDPatternOperator IdentityVec>
+ : MVE_VADDSUB_fp_m<"vsub", 1, VTI, fsub, int_arm_mve_sub_predicated, IdentityVec>;
-defm MVE_VADDf32 : MVE_VADD_fp_m<MVE_v4f32>;
-defm MVE_VADDf16 : MVE_VADD_fp_m<MVE_v8f16>;
+def ARMimmMinusZeroF: PatLeaf<(bitconvert (v4i32 (ARMvmovImm (i32 1664))))>; // -0.0 float
+def ARMimmMinusZeroH: PatLeaf<(bitconvert (v8i16 (ARMvmovImm (i32 2688))))>; // -0.0 half
-defm MVE_VSUBf32 : MVE_VSUB_fp_m<MVE_v4f32>;
-defm MVE_VSUBf16 : MVE_VSUB_fp_m<MVE_v8f16>;
+defm MVE_VADDf32 : MVE_VADD_fp_m<MVE_v4f32, ARMimmMinusZeroF>;
+defm MVE_VADDf16 : MVE_VADD_fp_m<MVE_v8f16, ARMimmMinusZeroH>;
+
+defm MVE_VSUBf32 : MVE_VSUB_fp_m<MVE_v4f32, ARMimmAllZerosV>;
+defm MVE_VSUBf16 : MVE_VSUB_fp_m<MVE_v8f16, ARMimmAllZerosV>;
class MVE_VCADD<string suffix, bits<2> size, string cstr="">
: MVEFloatArithNeon<"vcadd", suffix, size{1}, (outs MQPR:$Qd),
@@ -5373,22 +5379,22 @@ defm MVE_VHSUB_qr_u16 : MVE_VHSUB_qr_m<MVE_v8u16>;
defm MVE_VHSUB_qr_u32 : MVE_VHSUB_qr_m<MVE_v4u32>;
multiclass MVE_VADDSUB_qr_f<string iname, MVEVectorVTInfo VTI, bit subtract,
- SDNode Op, Intrinsic PredInt> {
+ SDNode Op, Intrinsic PredInt, SDPatternOperator IdentityVec> {
def "" : MVE_VxADDSUB_qr<iname, VTI.Suffix, VTI.Size{0}, 0b11, subtract, VTI.Size>;
defm : MVE_TwoOpPatternDup<VTI, Op, PredInt, (? ),
- !cast<Instruction>(NAME)>;
+ !cast<Instruction>(NAME), IdentityVec>;
}
let Predicates = [HasMVEFloat] in {
defm MVE_VADD_qr_f32 : MVE_VADDSUB_qr_f<"vadd", MVE_v4f32, 0b0, fadd,
- int_arm_mve_add_predicated>;
+ int_arm_mve_add_predicated, ARMimmMinusZeroF>;
defm MVE_VADD_qr_f16 : MVE_VADDSUB_qr_f<"vadd", MVE_v8f16, 0b0, fadd,
- int_arm_mve_add_predicated>;
+ int_arm_mve_add_predicated, ARMimmMinusZeroH>;
defm MVE_VSUB_qr_f32 : MVE_VADDSUB_qr_f<"vsub", MVE_v4f32, 0b1, fsub,
- int_arm_mve_sub_predicated>;
+ int_arm_mve_sub_predicated, ARMimmAllZerosV>;
defm MVE_VSUB_qr_f16 : MVE_VADDSUB_qr_f<"vsub", MVE_v8f16, 0b1, fsub,
- int_arm_mve_sub_predicated>;
+ int_arm_mve_sub_predicated, ARMimmAllZerosV>;
}
class MVE_VxSHL_qr<string iname, string suffix, bit U, bits<2> size,
@@ -5567,16 +5573,16 @@ defm MVE_VQRDMULH_qr_s8 : MVE_VQRDMULH_qr_m<MVE_v16s8>;
defm MVE_VQRDMULH_qr_s16 : MVE_VQRDMULH_qr_m<MVE_v8s16>;
defm MVE_VQRDMULH_qr_s32 : MVE_VQRDMULH_qr_m<MVE_v4s32>;
-multiclass MVE_VxxMUL_qr_f_m<MVEVectorVTInfo VTI> {
+multiclass MVE_VxxMUL_qr_f_m<MVEVectorVTInfo VTI, SDPatternOperator IdentityVec> {
let validForTailPredication = 1 in
def "" : MVE_VxxMUL_qr<"vmul", VTI.Suffix, VTI.Size{0}, 0b11, VTI.Size>;
defm : MVE_TwoOpPatternDup<VTI, fmul, int_arm_mve_mul_predicated, (? ),
- !cast<Instruction>(NAME)>;
+ !cast<Instruction>(NAME), IdentityVec>;
}
let Predicates = [HasMVEFloat] in {
- defm MVE_VMUL_qr_f16 : MVE_VxxMUL_qr_f_m<MVE_v8f16>;
- defm MVE_VMUL_qr_f32 : MVE_VxxMUL_qr_f_m<MVE_v4f32>;
+ defm MVE_VMUL_qr_f16 : MVE_VxxMUL_qr_f_m<MVE_v8f16, ARMimmOneH>;
+ defm MVE_VMUL_qr_f32 : MVE_VxxMUL_qr_f_m<MVE_v4f32, ARMimmOneF>;
}
class MVE_VFMAMLA_qr<string iname, string suffix,
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-selectop3.ll b/llvm/test/CodeGen/Thumb2/mve-pred-selectop3.ll
index 2ad93c4b19c47..238133c21e207 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-selectop3.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-selectop3.ll
@@ -352,11 +352,9 @@ entry:
define arm_aapcs_vfpcc <4 x float> @fadd_v4f32_x(<4 x float> %x, <4 x float> %y, i32 %n) {
; CHECK-LABEL: fadd_v4f32_x:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i32 q2, #0x80000000
; CHECK-NEXT: vctp.32 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vmovt q2, q1
-; CHECK-NEXT: vadd.f32 q0, q2, q0
+; CHECK-NEXT: vaddt.f32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
@@ -368,11 +366,9 @@ entry:
define arm_aapcs_vfpcc <8 x half> @fadd_v8f16_x(<8 x half> %x, <8 x half> %y, i32 %n) {
; CHECK-LABEL: fadd_v8f16_x:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i16 q2, #0x8000
; CHECK-NEXT: vctp.16 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vmovt q2, q1
-; CHECK-NEXT: vadd.f16 q0, q2, q0
+; CHECK-NEXT: vaddt.f16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
@@ -384,11 +380,9 @@ entry:
define arm_aapcs_vfpcc <4 x float> @fsub_v4f32_x(<4 x float> %x, <4 x float> %y, i32 %n) {
; CHECK-LABEL: fsub_v4f32_x:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i32 q2, #0x0
; CHECK-NEXT: vctp.32 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vmovt q2, q1
-; CHECK-NEXT: vsub.f32 q0, q0, q2
+; CHECK-NEXT: vsubt.f32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
@@ -400,11 +394,9 @@ entry:
define arm_aapcs_vfpcc <8 x half> @fsub_v8f16_x(<8 x half> %x, <8 x half> %y, i32 %n) {
; CHECK-LABEL: fsub_v8f16_x:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i32 q2, #0x0
; CHECK-NEXT: vctp.16 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vmovt q2, q1
-; CHECK-NEXT: vsub.f16 q0, q0, q2
+; CHECK-NEXT: vsubt.f16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
@@ -416,11 +408,9 @@ entry:
define arm_aapcs_vfpcc <4 x float> @fmul_v4f32_x(<4 x float> %x, <4 x float> %y, i32 %n) {
; CHECK-LABEL: fmul_v4f32_x:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.f32 q2, #1.000000e+00
; CHECK-NEXT: vctp.32 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vmovt q2, q1
-; CHECK-NEXT: vmul.f32 q0, q2, q0
+; CHECK-NEXT: vmult.f32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
@@ -432,11 +422,9 @@ entry:
define arm_aapcs_vfpcc <8 x half> @fmul_v8f16_x(<8 x half> %x, <8 x half> %y, i32 %n) {
; CHECK-LABEL: fmul_v8f16_x:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i16 q2, #0x3c00
; CHECK-NEXT: vctp.16 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vmovt q2, q1
-; CHECK-NEXT: vmul.f16 q0, q2, q0
+; CHECK-NEXT: vmult.f16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
@@ -482,11 +470,10 @@ entry:
define arm_aapcs_vfpcc <4 x float> @fma_v4f32_x(<4 x float> %x, <4 x float> %y, <4 x float> %z, i32 %n) {
; CHECK-LABEL: fma_v4f32_x:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i32 q3, #0x80000000
+; CHECK-NEXT: vmul.f32 q1, q1, q2
; CHECK-NEXT: vctp.32 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vmult.f32 q3, q1, q2
-; CHECK-NEXT: vadd.f32 q0, q3, q0
+; CHECK-NEXT: vaddt.f32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
@@ -499,11 +486,10 @@ entry:
define arm_aapcs_vfpcc <8 x half> @fma_v8f16_x(<8 x half> %x, <8 x half> %y, <8 x half> %z, i32 %n) {
; CHECK-LABEL: fma_v8f16_x:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i16 q3, #0x8000
+; CHECK-NEXT: vmul.f16 q1, q1, q2
; CHECK-NEXT: vctp.16 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vmult.f16 q3, q1, q2
-; CHECK-NEXT: vadd.f16 q0, q3, q0
+; CHECK-NEXT: vaddt.f16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
@@ -1068,12 +1054,10 @@ entry:
define arm_aapcs_vfpcc <4 x float> @faddqr_v4f32_x(<4 x float> %x, float %y, i32 %n) {
; CHECK-LABEL: faddqr_v4f32_x:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i32 q2, #0x80000000
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: vctp.32 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vdupt.32 q2, r1
-; CHECK-NEXT: vadd.f32 q0, q2, q0
+; CHECK-NEXT: vaddt.f32 q0, q0, r1
; CHECK-NEXT: bx lr
entry:
%c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
@@ -1088,11 +1072,9 @@ define arm_aapcs_vfpcc <8 x half> @faddqr_v8f16_x(<8 x half> %x, half %y, i32 %n
; CHECK-LABEL: faddqr_v8f16_x:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f16 r1, s4
-; CHECK-NEXT: vmov.i16 q1, #0x8000
; CHECK-NEXT: vctp.16 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vdupt.16 q1, r1
-; CHECK-NEXT: vadd.f16 q0, q1, q0
+; CHECK-NEXT: vaddt.f16 q0, q0, r1
; CHECK-NEXT: bx lr
entry:
%c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
@@ -1106,12 +1088,10 @@ entry:
define arm_aapcs_vfpcc <4 x float> @fsubqr_v4f32_x(<4 x float> %x, float %y, i32 %n) {
; CHECK-LABEL: fsubqr_v4f32_x:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i32 q2, #0x0
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: vctp.32 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vdupt.32 q2, r1
-; CHECK-NEXT: vsub.f32 q0, q0, q2
+; CHECK-NEXT: vsubt.f32 q0, q0, r1
; CHECK-NEXT: bx lr
entry:
%c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
@@ -1126,11 +1106,9 @@ define arm_aapcs_vfpcc <8 x half> @fsubqr_v8f16_x(<8 x half> %x, half %y, i32 %n
; CHECK-LABEL: fsubqr_v8f16_x:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f16 r1, s4
-; CHECK-NEXT: vmov.i32 q1, #0x0
; CHECK-NEXT: vctp.16 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vdupt.16 q1, r1
-; CHECK-NEXT: vsub.f16 q0, q0, q1
+; CHECK-NEXT: vsubt.f16 q0, q0, r1
; CHECK-NEXT: bx lr
entry:
%c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
@@ -1144,12 +1122,10 @@ entry:
define arm_aapcs_vfpcc <4 x float> @fmulqr_v4f32_x(<4 x float> %x, float %y, i32 %n) {
; CHECK-LABEL: fmulqr_v4f32_x:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.f32 q2, #1.000000e+00
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: vctp.32 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vdupt.32 q2, r1
-; CHECK-NEXT: vmul.f32 q0, q2, q0
+; CHECK-NEXT: vmult.f32 q0, q0, r1
; CHECK-NEXT: bx lr
entry:
%c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
@@ -1164,11 +1140,9 @@ define arm_aapcs_vfpcc <8 x half> @fmulqr_v8f16_x(<8 x half> %x, half %y, i32 %n
; CHECK-LABEL: fmulqr_v8f16_x:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f16 r1, s4
-; CHECK-NEXT: vmov.i16 q1, #0x3c00
; CHECK-NEXT: vctp.16 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vdupt.16 q1, r1
-; CHECK-NEXT: vmul.f16 q0, q1, q0
+; CHECK-NEXT: vmult.f16 q0, q0, r1
; CHECK-NEXT: bx lr
entry:
%c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
@@ -1740,11 +1714,10 @@ entry:
define arm_aapcs_vfpcc <4 x float> @fadd_v4f32_y(<4 x float> %x, <4 x float> %y, i32 %n) {
; CHECK-LABEL: fadd_v4f32_y:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i32 q2, #0x80000000
; CHECK-NEXT: vctp.32 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vmovt q2, q0
-; CHECK-NEXT: vadd.f32 q0, q2, q1
+; CHECK-NEXT: vaddt.f32 q1, q1, q0
+; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
entry:
%c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
@@ -1756,11 +1729,10 @@ entry:
define arm_aapcs_vfpcc <8 x half> @fadd_v8f16_y(<8 x half> %x, <8 x half> %y, i32 %n) {
; CHECK-LABEL: fadd_v8f16_y:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i16 q2, #0x8000
; CHECK-NEXT: vctp.16 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vmovt q2, q0
-; CHECK-NEXT: vadd.f16 q0, q2, q1
+; CHECK-NEXT: vaddt.f16 q1, q1, q0
+; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
entry:
%c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
@@ -1802,11 +1774,10 @@ entry:
define arm_aapcs_vfpcc <4 x float> @fmul_v4f32_y(<4 x float> %x, <4 x float> %y, i32 %n) {
; CHECK-LABEL: fmul_v4f32_y:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.f32 q2, #1.000000e+00
; CHECK-NEXT: vctp.32 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vmovt q2, q0
-; CHECK-NEXT: vmul.f32 q0, q2, q1
+; CHECK-NEXT: vmult.f32 q1, q1, q0
+; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
entry:
%c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
@@ -1818,11 +1789,10 @@ entry:
define arm_aapcs_vfpcc <8 x half> @fmul_v8f16_y(<8 x half> %x, <8 x half> %y, i32 %n) {
; CHECK-LABEL: fmul_v8f16_y:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i16 q2, #0x3c00
; CHECK-NEXT: vctp.16 r0
; CHECK-NEXT: vpst
-; CHECK-NEXT: vmovt q2, q0
-; CHECK-NEXT: vmul.f16 q0, q2, q1
+; CHECK-NEXT: vmult.f16 q1, q1, q0
+; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
entry:
%c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
@@ -2448,12 +2418,12 @@ entry:
define arm_aapcs_vfpcc <4 x float> @faddqr_v4f32_y(<4 x float> %x, float %y, i32 %n) {
; CHECK-LABEL: faddqr_v4f32_y:
; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: vctp.32 r0
-; CHECK-NEXT: vmov.i32 q2, #0x80000000
+; CHECK-NEXT: vdup.32 q1, r1
; CHECK-NEXT: vpst
-; CHECK-NEXT: vmovt q2, q0
-; CHECK-NEXT: vmov r0, s4
-; CHECK-NEXT: vadd.f32 q0, q2, r0
+; CHECK-NEXT: vaddt.f32 q1, q1, q0
+; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
entry:
%c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
@@ -2467,12 +2437,12 @@ entry:
define arm_aapcs_vfpcc <8 x half> @faddqr_v8f16_y(<8 x half> %x, half %y, i32 %n) {
; CHECK-LABEL: faddqr_v8f16_y:
; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.f16 r1, s4
; CHECK-NEXT: vctp.16 r0
-; CHECK-NEXT: vmov.i16 q2, #0x8000
+; CHECK-NEXT: vdup.16 q1, r1
; CHECK-NEXT: vpst
-; CHECK-NEXT: vmovt q2, q0
-; CHECK-NEXT: vmov.f16 r0, s4
-; CHECK-NEXT: vadd.f16 q0, q2, r0
+; CHECK-NEXT: vaddt.f16 q1, q1, q0
+; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
entry:
%c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
@@ -2524,12 +2494,12 @@ entry:
define arm_aapcs_vfpcc <4 x float> @fmulqr_v4f32_y(<4 x float> %x, float %y, i32 %n) {
; CHECK-LABEL: fmulqr_v4f32_y:
; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: vctp.32 r0
-; CHECK-NEXT: vmov.f32 q2, #1.000000e+00
+; CHECK-NEXT: vdup.32 q1, r1
; CHECK-NEXT: vpst
-; CHECK-NEXT: vmovt q2, q0
-; CHECK-NEXT: vmov r0, s4
-; CHECK-NEXT: vmul.f32 q0, q2, r0
+; CHECK-NEXT: vmult.f32 q1, q1, q0
+; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
entry:
%c = call <4 x i1> @llvm.arm.mve.vctp32(i32 %n)
@@ -2543,12 +2513,12 @@ entry:
define arm_aapcs_vfpcc <8 x half> @fmulqr_v8f16_y(<8 x half> %x, half %y, i32 %n) {
; CHECK-LABEL: fmulqr_v8f16_y:
; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.f16 r1, s4
; CHECK-NEXT: vctp.16 r0
-; CHECK-NEXT: vmov.i16 q2, #0x3c00
+; CHECK-NEXT: vdup.16 q1, r1
; CHECK-NEXT: vpst
-; CHECK-NEXT: vmovt q2, q0
-; CHECK-NEXT: vmov.f16 r0, s4
-; CHECK-NEXT: vmul.f16 q0, q2, r0
+; CHECK-NEXT: vmult.f16 q1, q1, q0
+; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
entry:
%c = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
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