[PATCH] D114232: [AMDGPU] Fold more inline constant operands by commuting instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir:18
+    ; CHECK-NEXT: [[V_ADDC_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADDC_U32_e32 0, [[COPY]], implicit-def $vcc, implicit $vcc, implicit $exec
+    ; CHECK-NEXT: [[V_ADDC_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADDC_U32_e32 0, [[COPY1]], implicit-def $vcc, implicit $vcc, implicit $exec
+    ; CHECK-NEXT: S_NOP 0, implicit [[V_ADDC_U32_e32_]], implicit [[V_ADDC_U32_e32_1]]
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foad wrote:
> It occurs to me now that SIFoldOperands would probably have succeeded here if these were using the e64 form of the instruction. But there are obviously real world cases where it sees the e32 form, otherwise none of the .ll tests would have been improved by this patch.
> 
> Is it worth abandoning this patch and pursuing why we are selecting e32 instructions in the first place?
I don't know about abandoning, but it should be looked into. We're mostly consistent in picking the e64 forms upfront


Repository:
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  https://reviews.llvm.org/D114232/new/

https://reviews.llvm.org/D114232