[llvm] d45cb1d - [llvm] Use range-based for loops (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 23 08:54:58 PST 2021
Author: Kazu Hirata
Date: 2021-11-23T08:54:48-08:00
New Revision: d45cb1d7ea911f43922c7f07e2c819cc8592a70d
URL: https://github.com/llvm/llvm-project/commit/d45cb1d7ea911f43922c7f07e2c819cc8592a70d
DIFF: https://github.com/llvm/llvm-project/commit/d45cb1d7ea911f43922c7f07e2c819cc8592a70d.diff
LOG: [llvm] Use range-based for loops (NFC)
Added:
Modified:
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
llvm/lib/CodeGen/LiveVariables.cpp
llvm/lib/CodeGen/RegisterCoalescer.cpp
llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 3a52959d54bfe..df629b40df6e5 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -3825,8 +3825,7 @@ bool CombinerHelper::matchExtractAllEltsFromBuildVector(
unsigned NumElts = DstTy.getNumElements();
SmallBitVector ExtractedElts(NumElts);
- for (auto &II : make_range(MRI.use_instr_nodbg_begin(DstReg),
- MRI.use_instr_nodbg_end())) {
+ for (MachineInstr &II : MRI.use_nodbg_instructions(DstReg)) {
if (II.getOpcode() != TargetOpcode::G_EXTRACT_VECTOR_ELT)
return false;
auto Cst = getIConstantVRegVal(II.getOperand(2).getReg(), MRI);
diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index 51ba4b7e53eba..e8744797707b0 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -58,9 +58,9 @@ void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
MachineInstr *
LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const {
- for (unsigned i = 0, e = Kills.size(); i != e; ++i)
- if (Kills[i]->getParent() == MBB)
- return Kills[i];
+ for (MachineInstr *MI : Kills)
+ if (MI->getParent() == MBB)
+ return MI;
return nullptr;
}
@@ -811,8 +811,8 @@ bool LiveVariables::isLiveOut(Register Reg, const MachineBasicBlock &MBB) {
LiveVariables::VarInfo &VI = getVarInfo(Reg);
SmallPtrSet<const MachineBasicBlock *, 8> Kills;
- for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
- Kills.insert(VI.Kills[i]->getParent());
+ for (MachineInstr *MI : VI.Kills)
+ Kills.insert(MI->getParent());
// Loop over all of the successors of the basic block, checking to see if
// the value is either live in the block, or if it is killed in the block.
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index c847068bca908..4c8534cf2d018 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -3908,20 +3908,20 @@ void RegisterCoalescer::lateLiveIntervalUpdate() {
bool RegisterCoalescer::
copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList) {
bool Progress = false;
- for (unsigned i = 0, e = CurrList.size(); i != e; ++i) {
- if (!CurrList[i])
+ for (MachineInstr *&MI : CurrList) {
+ if (!MI)
continue;
// Skip instruction pointers that have already been erased, for example by
// dead code elimination.
- if (ErasedInstrs.count(CurrList[i])) {
- CurrList[i] = nullptr;
+ if (ErasedInstrs.count(MI)) {
+ MI = nullptr;
continue;
}
bool Again = false;
- bool Success = joinCopy(CurrList[i], Again);
+ bool Success = joinCopy(MI, Again);
Progress |= Success;
if (Success || !Again)
- CurrList[i] = nullptr;
+ MI = nullptr;
}
return Progress;
}
diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
index 6f63f686635a5..582f6b272df3b 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
@@ -497,8 +497,7 @@ char SIWholeQuadMode::scanInstructions(MachineFunction &MF,
MachineBasicBlock &MBB = **BI;
BlockInfo &BBI = Blocks[&MBB];
- for (auto II = MBB.begin(), IE = MBB.end(); II != IE; ++II) {
- MachineInstr &MI = *II;
+ for (MachineInstr &MI : MBB) {
InstrInfo &III = Instructions[&MI];
unsigned Opcode = MI.getOpcode();
char Flags = 0;
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index 121558276c3e1..070066fd9468f 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -2211,8 +2211,7 @@ bool ARMConstantIslands::optimizeThumb2JumpTables() {
unsigned JTOffset = BBUtils->getOffsetOf(MI) + 4;
const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
BBInfoVector &BBInfo = BBUtils->getBBInfo();
- for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) {
- MachineBasicBlock *MBB = JTBBs[j];
+ for (MachineBasicBlock *MBB : JTBBs) {
unsigned DstOffset = BBInfo[MBB->getNumber()].Offset;
// Negative offset is not ok. FIXME: We should change BB layout to make
// sure all the branches are forward.
@@ -2405,8 +2404,7 @@ bool ARMConstantIslands::reorderThumb2JumpTables() {
// and try to adjust them such that that's true.
int JTNumber = MI->getParent()->getNumber();
const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
- for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) {
- MachineBasicBlock *MBB = JTBBs[j];
+ for (MachineBasicBlock *MBB : JTBBs) {
int DTNumber = MBB->getNumber();
if (DTNumber < JTNumber) {
@@ -2415,7 +2413,7 @@ bool ARMConstantIslands::reorderThumb2JumpTables() {
MachineBasicBlock *NewBB =
adjustJTTargetBlockForward(MBB, MI->getParent());
if (NewBB)
- MJTI->ReplaceMBBInJumpTable(JTI, JTBBs[j], NewBB);
+ MJTI->ReplaceMBBInJumpTable(JTI, MBB, NewBB);
MadeChange = true;
}
}
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index e7e10ce07a44f..239e2270966f2 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -10587,10 +10587,9 @@ void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
LPadList.reserve(CallSiteNumToLPad.size());
for (unsigned I = 1; I <= MaxCSNum; ++I) {
SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
- for (SmallVectorImpl<MachineBasicBlock*>::iterator
- II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
- LPadList.push_back(*II);
- InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
+ for (MachineBasicBlock *MBB : MBBList) {
+ LPadList.push_back(MBB);
+ InvokeBBs.insert(MBB->pred_begin(), MBB->pred_end());
}
}
@@ -10879,9 +10878,7 @@ void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
// Add the jump table entries as successors to the MBB.
SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
- for (std::vector<MachineBasicBlock*>::iterator
- I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
- MachineBasicBlock *CurMBB = *I;
+ for (MachineBasicBlock *CurMBB : LPadList) {
if (SeenMBBs.insert(CurMBB).second)
DispContBB->addSuccessor(CurMBB);
}
@@ -10943,9 +10940,8 @@ void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
// Mark all former landing pads as non-landing pads. The dispatch is the only
// landing pad now.
- for (SmallVectorImpl<MachineBasicBlock*>::iterator
- I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
- (*I)->setIsEHPad(false);
+ for (MachineBasicBlock *MBBLPad : MBBLPads)
+ MBBLPad->setIsEHPad(false);
// The instruction is gone now.
MI.eraseFromParent();
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 6e259b1baf97f..96f80cd38eccc 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -2119,9 +2119,7 @@ bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
isThumb1 = AFI->isThumbFunction() && !isThumb2;
bool Modified = false;
- for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
- ++MFI) {
- MachineBasicBlock &MBB = *MFI;
+ for (MachineBasicBlock &MBB : Fn) {
Modified |= LoadStoreMultipleOpti(MBB);
if (STI->hasV5TOps())
Modified |= MergeReturnIntoLDM(MBB);
diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
index def877409444b..0ad06934898bf 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
@@ -1451,8 +1451,7 @@ bool HexagonGenInsert::removeDeadCode(MachineDomTreeNode *N) {
for (auto I = B->rbegin(), E = B->rend(); I != E; ++I)
Instrs.push_back(&*I);
- for (auto I = Instrs.begin(), E = Instrs.end(); I != E; ++I) {
- MachineInstr *MI = *I;
+ for (MachineInstr *MI : Instrs) {
unsigned Opc = MI->getOpcode();
// Do not touch lifetime markers. This is why the target-independent DCE
// cannot be used.
diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
index e22836823b880..1a66394e97573 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
@@ -486,8 +486,8 @@ bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) {
}
}
- for (VectOfInst::iterator I = Erase.begin(), E = Erase.end(); I != E; ++I)
- (*I)->eraseFromParent();
+ for (MachineInstr *MI : Erase)
+ MI->eraseFromParent();
return Changed;
}
@@ -513,11 +513,8 @@ bool HexagonGenPredicate::runOnMachineFunction(MachineFunction &MF) {
Again = false;
VectOfInst Processed, Copy;
- using iterator = VectOfInst::iterator;
-
Copy = PUsers;
- for (iterator I = Copy.begin(), E = Copy.end(); I != E; ++I) {
- MachineInstr *MI = *I;
+ for (MachineInstr *MI : Copy) {
bool Done = convertToPredForm(MI);
if (Done) {
Processed.insert(MI);
diff --git a/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp b/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp
index 93ba277b0c9d0..2c5c64cfcfc65 100644
--- a/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp
@@ -400,8 +400,7 @@ bool HexagonStoreWidening::createWideStores(InstrGroup &OG, InstrGroup &NG,
unsigned Acc = 0; // Value accumulator.
unsigned Shift = 0;
- for (InstrGroup::iterator I = OG.begin(), E = OG.end(); I != E; ++I) {
- MachineInstr *MI = *I;
+ for (MachineInstr *MI : OG) {
const MachineMemOperand &MMO = getStoreTarget(MI);
MachineOperand &SO = MI->getOperand(2); // Source.
assert(SO.isImm() && "Expecting an immediate operand");
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