[PATCH] D114361: [MachineCSE] Add an option to enable global CSE
ChenZheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 23 05:14:03 PST 2021
shchenz added inline comments.
================
Comment at: llvm/lib/CodeGen/MachineCSE.cpp:440
+ TII->enableAggressiveMachineCSE(*MI->getMF()))
+ return true;
+
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If the register pressure is increased, doing more CSEs may introduce register spill/reload and thus it will generate worse code even for optimization for size?
================
Comment at: llvm/lib/CodeGen/MachineCSE.cpp:468
if (CSBB != BB && !CSBB->isSuccessor(BB))
return false;
}
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Can we estimate the register pressure here to do a more aggressive CSE? If so, we should not limit this only for "optimization for size".
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D114361/new/
https://reviews.llvm.org/D114361
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