[PATCH] D113281: [AArch64][SVE] Generate ASRD instructions for power of 2 signed divides

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm accepted this revision.
peterwaller-arm added a comment.
This revision is now accepted and ready to land.

Looks good with one minor suggestion from me.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:13591
+
+  MVT ConstType = VT.getVectorElementType() == MVT::i64 ? MVT::i64 : MVT::i32;
+
----------------
Nit/suggestion: Please add a comment showing the form of the combine.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D113281/new/

https://reviews.llvm.org/D113281