[PATCH] D114354: [DAG] SimplifyDemandedBits - simplify rotl/rotr to shl/srl

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1749-1755
+      // See if we don't demand either half of the rotated bits.
+      if ((!TLO.LegalOperations() || isOperationLegal(ISD::SHL, VT)) &&
+          DemandedBits.countTrailingZeros() >= (IsROTL ? RevAmt : Amt)) {
+        if (!IsROTL)
+          Op1 = TLO.DAG.getConstant(RevAmt, dl, Op1.getValueType());
+        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT, Op0, Op1));
+      }
----------------
lebedev.ri wrote:
> Are you sure this is right?
> https://alive2.llvm.org/ce/z/EJDzlC
Perhaps this is what you had in mind:
* https://alive2.llvm.org/ce/z/iroxki (rol -> shl by amt iff demanded bits has at least as many trailing zeros as the shift amount)
* https://alive2.llvm.org/ce/z/4ez_U- (ror -> shl by revamt iff demanded bits has at least as many trailing zeros as the reverse shift amount)
* https://alive2.llvm.org/ce/z/cD7dR- (ror -> lshr by amt iff demanded bits has at least as many leading zeros as the shift amount)
* https://alive2.llvm.org/ce/z/_XGHtQ (rol -> lshr by revamt iff demanded bits has at least as many leading zeros as the reverse shift amount)


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114354/new/

https://reviews.llvm.org/D114354