[llvm] dc9b555 - [NFC][llvm][Hexagon] Inclusive Terms remove uses of sanity in Hexagon taget
Zarko Todorovski via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 22 07:08:06 PST 2021
Author: Zarko Todorovski
Date: 2021-11-22T10:08:01-05:00
New Revision: dc9b5550b2238d65bcaa937c412d51802d819aeb
URL: https://github.com/llvm/llvm-project/commit/dc9b5550b2238d65bcaa937c412d51802d819aeb
DIFF: https://github.com/llvm/llvm-project/commit/dc9b5550b2238d65bcaa937c412d51802d819aeb.diff
LOG: [NFC][llvm][Hexagon] Inclusive Terms remove uses of sanity in Hexagon taget
Most changes are rewording comments but there are some assertions that I rephrased.
Reviewed By: kparzysz
Differential Revision: https://reviews.llvm.org/D114132
Added:
Modified:
llvm/lib/Target/Hexagon/BitTracker.cpp
llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
llvm/lib/Target/Hexagon/HexagonGenMux.cpp
llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
llvm/test/CodeGen/Hexagon/abi-padding-2.ll
llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp
index 8bced3cec082f..0f6c10a6256c9 100644
--- a/llvm/lib/Target/Hexagon/BitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/BitTracker.cpp
@@ -214,9 +214,9 @@ bool BT::RegisterCell::meet(const RegisterCell &RC, Register SelfR) {
BT::RegisterCell &BT::RegisterCell::insert(const BT::RegisterCell &RC,
const BitMask &M) {
uint16_t B = M.first(), E = M.last(), W = width();
- // Sanity: M must be a valid mask for *this.
+ // M must be a valid mask for *this.
assert(B < W && E < W);
- // Sanity: the masked part of *this must have the same number of bits
+ // The masked part of *this must have the same number of bits
// as the source.
assert(B > E || E-B+1 == RC.width()); // B <= E => E-B+1 = |RC|.
assert(B <= E || E+(W-B)+1 == RC.width()); // E < B => E+(W-B)+1 = |RC|.
diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
index 0f6dedeb28c3b..1938a5c259da9 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
@@ -189,7 +189,7 @@ bool HexagonEvaluator::evaluate(const MachineInstr &MI,
unsigned NumDefs = 0;
- // Sanity verification: there should not be any defs with subregisters.
+ // Basic correctness check: there should not be any defs with subregisters.
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
diff --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
index a774baaa48e62..d3fcdb6ae9a85 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
@@ -1254,7 +1254,7 @@ void HCE::collect(MachineFunction &MF) {
void HCE::assignInits(const ExtRoot &ER, unsigned Begin, unsigned End,
AssignmentMap &IMap) {
- // Sanity check: make sure that all extenders in the range [Begin..End)
+ // Basic correctness: make sure that all extenders in the range [Begin..End)
// share the same root ER.
for (unsigned I = Begin; I != End; ++I)
assert(ER == ExtRoot(Extenders[I].getOp()));
diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
index 02da2f29591a5..d7908085eec0c 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
@@ -1501,7 +1501,7 @@ bool HexagonGenInsert::runOnMachineFunction(MachineFunction &MF) {
bool Timing = OptTiming, TimingDetail = Timing && OptTimingDetail;
bool Changed = false;
- // Sanity check: one, but not both.
+ // Verify: one, but not both.
assert(!OptSelectAll0 || !OptSelectHas0);
IFMap.clear();
diff --git a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
index cf4f13fb8c0d3..55de02816fb8d 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
@@ -328,7 +328,7 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) {
unsigned MxOpc = getMuxOpcode(*MX.SrcT, *MX.SrcF);
if (!MxOpc)
continue;
- // Basic sanity check: since we are deleting instructions, validate the
+ // Basic correctness check: since we are deleting instructions, validate the
// iterators. There is a possibility that one of Def1 or Def2 is translated
// to "mux" and being considered for other "mux" instructions.
if (!MX.At->getParent() || !MX.Def1->getParent() || !MX.Def2->getParent())
diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
index d8d2025c5d27e..ac7813c7190af 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
@@ -411,7 +411,7 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) {
NumOps = 2;
}
- // Some sanity: check that def is in operand #0.
+ // Check that def is in operand #0.
MachineOperand &Op0 = MI->getOperand(0);
assert(Op0.isDef());
RegisterSubReg OutR(Op0);
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index a4971ad712eb9..3ac1a97a5ff6e 100644
--- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -1123,7 +1123,7 @@ void HexagonHardwareLoops::removeIfDead(MachineInstr *MI) {
bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L,
bool &RecL0used,
bool &RecL1used) {
- // This is just for sanity.
+ // This is just to confirm basic correctness.
assert(L->getHeader() && "Loop without a header?");
bool Changed = false;
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
index b50a0e29ecae7..ed4874baf7c82 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
@@ -1006,7 +1006,7 @@ static void packSegmentMask(ArrayRef<int> Mask, ArrayRef<unsigned> OutSegMap,
static bool isPermutation(ArrayRef<int> Mask) {
// Check by adding all numbers only works if there is no overflow.
- assert(Mask.size() < 0x00007FFF && "Sanity failure");
+ assert(Mask.size() < 0x00007FFF && "Overflow failure");
int Sum = 0;
for (int Idx : Mask) {
if (Idx == -1)
@@ -1217,7 +1217,7 @@ OpRef HvxSelector::packs(ShuffleMask SM, OpRef Va, OpRef Vb,
} else if (Seg0 == ~1u) {
Seg0 = SegList[0] != Seg1 ? SegList[0] : SegList[1];
} else {
- assert(Seg1 == ~1u); // Sanity
+ assert(Seg1 == ~1u);
Seg1 = SegList[0] != Seg0 ? SegList[0] : SegList[1];
}
}
@@ -1265,7 +1265,7 @@ OpRef HvxSelector::packs(ShuffleMask SM, OpRef Va, OpRef Vb,
} else {
// BC or DA: this could be done via valign by SegLen.
// Do nothing here, because valign (if possible) will be generated
- // later on (make sure the Seg0 values are as expected, for sanity).
+ // later on (make sure the Seg0 values are as expected).
assert(Seg0 == 1 || Seg0 == 3);
}
}
@@ -1414,7 +1414,7 @@ OpRef HvxSelector::shuffs1(ShuffleMask SM, OpRef Va, ResultStack &Results) {
return OpRef::undef(getSingleVT(MVT::i8));
unsigned HalfLen = HwLen / 2;
- assert(isPowerOf2_32(HalfLen)); // Sanity.
+ assert(isPowerOf2_32(HalfLen));
// Handle special case where the output is the same half of the input
// repeated twice, i.e. if Va = AB, then handle the output of AA or BB.
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 29572e3106d1d..ca61578c78489 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -2549,7 +2549,8 @@ HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV,
// Special case for v{8,4,2}i1 (the only boolean vectors legal in Hexagon
// without any coprocessors).
if (ElemWidth == 1) {
- assert(VecWidth == VecTy.getVectorNumElements() && "Sanity failure");
+ assert(VecWidth == VecTy.getVectorNumElements() &&
+ "Vector elements should equal vector width size");
assert(VecWidth == 8 || VecWidth == 4 || VecWidth == 2);
// Check if this is an extract of the lowest bit.
if (IdxN) {
@@ -2863,8 +2864,7 @@ HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
Scale /= 2;
}
- // Another sanity check. At this point there should only be two words
- // left, and Scale should be 2.
+ // At this point there should only be two words left, and Scale should be 2.
assert(Scale == 2 && Words[IdxW].size() == 2);
SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
diff --git a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
index 897fb209a8bfb..ea2798a3b44e5 100644
--- a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
@@ -749,7 +749,6 @@ auto AlignVectors::realignGroup(const MoveGroup &Move) const -> bool {
WithMaxAlign.ValTy, Adjust);
int Diff = Start - (OffAtMax + Adjust);
AlignVal = HVC.getConstInt(Diff);
- // Sanity.
assert(Diff >= 0);
assert(static_cast<decltype(MinNeeded.value())>(Diff) < MinNeeded.value());
} else {
diff --git a/llvm/test/CodeGen/Hexagon/abi-padding-2.ll b/llvm/test/CodeGen/Hexagon/abi-padding-2.ll
index 4bda4aed9c8b8..19d96a54f8633 100644
--- a/llvm/test/CodeGen/Hexagon/abi-padding-2.ll
+++ b/llvm/test/CodeGen/Hexagon/abi-padding-2.ll
@@ -14,7 +14,7 @@
; Test that while passing a 7-byte struct on the stack, the
; size of the struct is 16 bytes including padding since its
; largest member is of type long long. This was being handled
-; correctly but is a sanity check against any potential future
+; correctly but is a check against any potential future
; regressions.
;
diff --git a/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir b/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir
index e03b5b7bf2772..e3911ab0e6753 100644
--- a/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir
+++ b/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir
@@ -1,6 +1,6 @@
# RUN: llc < %s -x mir -march=hexagon -run-pass=modulo-schedule-test -pipeliner-experimental-cg=true | FileCheck %s
-# Simple check for this sanity test; ensure all instructions are in stage 0 in
+# Simple check for this basic correctness test; ensure all instructions are in stage 0 in
# the prolog and stage 3 in the epilog.
# CHECK-NOT: Stage-3
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