[PATCH] D114315: [X86][Costmodel] `getReplicationShuffleCost()`: promote 1 bit-wide elements to 32 bit when have AVX512DQ

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: llvm/lib/Target/X86/X86TargetTransformInfo.cpp:3707
+    if (ST->hasDQI()) {
+      PromEltTyBits = 32; // promote to i32, AVX512F.
+      break;
----------------
lebedev.ri wrote:
> RKSimon wrote:
> > lebedev.ri wrote:
> > > RKSimon wrote:
> > > > AVX512F or AVX512DQ?
> > > "<we can> promote to i32, AVX512F <then provides support for shuffling in that type>."
> > so why not promote for AVX512F only targets?
> I'm not sure i understand.
> 
> AVX512DQ is the instruction set that provides VPMOVM2[DQ] / VPMOV[DQ]2M instructions.
> Plain AVX512F does not provide any VPMOVM2. / VPMOV.2M instructions.
> So we need AVX512DQ for this.
> If we had AVX512BW/AVX512BW+VBMI, then we already chosen to promote to i16/i8.
In other words, are you saying that we should always promote to i1<->i32 as a fallback,
even if we don't necessarily have an instructions do to so? 


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  https://reviews.llvm.org/D114315/new/

https://reviews.llvm.org/D114315