[PATCH] D114258: [DebugInfo][1/N] Instruction referencing test changes: DBG_VALUE to DBG_INSTR_REF

Mon Nov 22 04:23:14 PST 2021

djtodoro added inline comments.

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Comment at: llvm/test/DebugInfo/X86/pr40427.ll:24
-; CHECK-NEXT: [[LOADR:%[0-9]+]]:gr16 = MOV16rm %0
-; CHECK-NEXT: DBG_VALUE [[LOADR]], $noreg, ![[DBGVAR]]
 ; CHECK-NEXT: %{{[0-9]+}}:gr32 = IMPLICIT_DEF
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jmorse wrote:
> jmorse wrote:
> > djtodoro wrote:
> > > Are we losing the test coverage for the DBG_VALUEs by doing this? I guess it is OK for the targets that will use this feature ON by default, right?
> > Yes and no -- the debug instruction placement code is shared between instruction referencing and DBG_VALUEs, so it's sort-of being covered. On the other hand, that might change, and I don't think any other architectures cover these parts of SelectionDAG.
> > 
> > I suppose I can leave the CHECK lines in from DBG_VALUE mode, and it's not going to harm anything / over-test, and that'll ensure that SelectionDAG is doing the right thing in DBG_VALUE mode, does that sound alright? (I'd prefer to not do that for the tests in the other patches)
> (... and to be clear, that preference is because as far as I'm aware, SelectionDAG is the only thing really shared between DBG_VALUE and instr-ref)
OK, sounds good to me. Let's add two checks for both modes in SelectionDAG.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114258/new/

https://reviews.llvm.org/D114258