[PATCH] D92105: [RISCV] Add pre-emit pass to make more instructions compressible

[Craig Blackmore via Phabricator via llvm-commits]

craigblackmore updated this revision to Diff 388866.
craigblackmore edited the summary of this revision.
craigblackmore added a comment.

Add support for LD/SD/FLW/FLD/FSW/FSD and address other inline comments from @jrtc27.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92105/new/

https://reviews.llvm.org/D92105

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVCompressInstrs.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/compress-instrs-i32-f-d.mir
  llvm/test/CodeGen/RISCV/compress-instrs-i64.mir

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