[PATCH] D114354: [DAG] SimplifyDemandedBits - simplify rotl/rotr to shl/srl

Simon Pilgrim via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Nov 22 03:07:19 PST 2021


RKSimon created this revision.
RKSimon added reviewers: spatel, lebedev.ri, nemanjai, t.p.northover, dmgreen, efriedma, uweigand, craig.topper.
Herald added subscribers: steven.zhang, pengfei, hiraditya, kristof.beyls.
RKSimon requested review of this revision.
Herald added a project: LLVM.

If we only demand bits from one half of a rotation pattern, see if we can simplify to a logical shift.

This changes a number of tests, some codegen changes look OK (x86 rotate + mask tests show the ability to remove both redundant shifts / masks), other changes (AArch64, PowerPC + SystemZ) are OK, or I've tweaked them to keep similar codegen.

That just leaves the ARM rev16 pattern, which I had to drop to prevent srl(bswap()) -> rotr(bswap) -> srl(bswap) infinite loops. I'm happy to add a ARM::REV16 opcode to prevent the regression, but wondered if the ARM gurus had any preferred alternatives?


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D114354

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/AArch64/rotate-extract.ll
  llvm/test/CodeGen/AArch64/urem-seteq.ll
  llvm/test/CodeGen/ARM/rev.ll
  llvm/test/CodeGen/ARM/sxt_rot.ll
  llvm/test/CodeGen/ARM/uxt_rot.ll
  llvm/test/CodeGen/ARM/uxtb.ll
  llvm/test/CodeGen/PowerPC/rlwinm2.ll
  llvm/test/CodeGen/SystemZ/risbg-01.ll
  llvm/test/CodeGen/SystemZ/risbg-04.ll
  llvm/test/CodeGen/Thumb2/thumb2-sxt_rot.ll
  llvm/test/CodeGen/Thumb2/thumb2-uxt_rot.ll
  llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll
  llvm/test/CodeGen/X86/rotate-extract-vector.ll
  llvm/test/CodeGen/X86/rotate-extract.ll
  llvm/test/CodeGen/X86/rotate_vec.ll
  llvm/test/CodeGen/X86/vector-rotate-128.ll
  llvm/test/CodeGen/X86/vector-rotate-256.ll
  llvm/test/CodeGen/X86/vector-rotate-512.ll

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