[PATCH] D114202: [AMDGPU] Fix SIPostRABundler crash on null register used by dbg value

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
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Recently we started generate DBG_VALUEs with $noreg operands.
This crashes SIPostRABundler, and it should not iterate these
registers anyway.


https://reviews.llvm.org/D114202

Files:
  llvm/lib/Target/AMDGPU/SIPostRABundler.cpp
  llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir


Index: llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
+++ llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
@@ -320,3 +320,21 @@
     KILL killed $vgpr5
     KILL killed $vgpr6
 ...
+
+---
+name: post_bundle_kill_and_null_reg_dbginfo
+body:             |
+  bb.0:
+    liveins: $vgpr3_vgpr4, $vgpr5_vgpr6
+
+    ; GCN-LABEL: name: post_bundle_kill_and_null_reg_dbginfo
+    ; GCN: BUNDLE implicit-def $vgpr0, implicit-def $vgpr0_lo16, implicit-def $vgpr0_hi16, implicit-def $vgpr1, implicit-def $vgpr1_lo16, implicit-def $vgpr1_hi16, implicit $vgpr3_vgpr4, implicit $exec, implicit $vgpr5_vgpr6 {
+    ; GCN-NEXT:   $vgpr0 = GLOBAL_LOAD_DWORD $vgpr3_vgpr4, 0, 0, implicit $exec
+    ; GCN-NEXT:   DBG_VALUE $noreg, $noreg
+    ; GCN-NEXT:   $vgpr1 = GLOBAL_LOAD_DWORD $vgpr5_vgpr6, 0, 0, implicit $exec
+    ; GCN-NEXT: }
+    $vgpr0 = GLOBAL_LOAD_DWORD $vgpr3_vgpr4, 0, 0, implicit $exec
+    DBG_VALUE $noreg, $noreg
+    $vgpr1 = GLOBAL_LOAD_DWORD $vgpr5_vgpr6, 0, 0, implicit $exec
+    KILL killed $vgpr3_vgpr4, killed $vgpr5_vgpr6
+...
Index: llvm/lib/Target/AMDGPU/SIPostRABundler.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIPostRABundler.cpp
+++ llvm/lib/Target/AMDGPU/SIPostRABundler.cpp
@@ -90,6 +90,9 @@
 
 void SIPostRABundler::collectUsedRegUnits(const MachineInstr &MI,
                                           BitVector &UsedRegUnits) const {
+  if (MI.isDebugInstr())
+    return;
+
   for (const MachineOperand &Op : MI.operands()) {
     if (!Op.isReg() || !Op.readsReg())
       continue;


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