[llvm] fc981ce - [llvm] Use range-based for loops (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 21 10:36:31 PST 2021
Author: Kazu Hirata
Date: 2021-11-21T10:36:18-08:00
New Revision: fc981cedea073519e25af04bcf85c50cb37cc2c9
URL: https://github.com/llvm/llvm-project/commit/fc981cedea073519e25af04bcf85c50cb37cc2c9
DIFF: https://github.com/llvm/llvm-project/commit/fc981cedea073519e25af04bcf85c50cb37cc2c9.diff
LOG: [llvm] Use range-based for loops (NFC)
Added:
Modified:
llvm/lib/CodeGen/PrologEpilogInserter.cpp
llvm/lib/Target/ARM/ARMFrameLowering.cpp
llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
llvm/lib/Target/MSP430/MSP430FrameLowering.cpp
llvm/lib/Target/Mips/Mips16FrameLowering.cpp
llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 9a4f70a6070f8..afc70a9c7343c 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -527,9 +527,9 @@ static void updateLiveness(MachineFunction &MF) {
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
MachineRegisterInfo &MRI = MF.getRegInfo();
- for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
+ for (const CalleeSavedInfo &I : CSI) {
for (MachineBasicBlock *MBB : Visited) {
- MCPhysReg Reg = CSI[i].getReg();
+ MCPhysReg Reg = I.getReg();
// Add the callee-saved register as live-in.
// It's killed at the spill.
if (!MRI.isReserved(Reg) && !MBB->isLiveIn(Reg))
@@ -540,17 +540,16 @@ static void updateLiveness(MachineFunction &MF) {
// each MBB between the prologue and epilogue so that it is not clobbered
// before it is reloaded in the epilogue. The Visited set contains all
// blocks outside of the region delimited by prologue/epilogue.
- if (CSI[i].isSpilledToReg()) {
+ if (I.isSpilledToReg()) {
for (MachineBasicBlock &MBB : MF) {
if (Visited.count(&MBB))
continue;
- MCPhysReg DstReg = CSI[i].getDstReg();
+ MCPhysReg DstReg = I.getDstReg();
if (!MBB.isLiveIn(DstReg))
MBB.addLiveIn(DstReg);
}
}
}
-
}
/// Insert restore code for the callee-saved registers used in the function.
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index 025e43444f9c5..71fa3e35eec2d 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -523,9 +523,9 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
}
// Determine spill area sizes.
- for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
- unsigned Reg = CSI[i].getReg();
- int FI = CSI[i].getFrameIdx();
+ for (const CalleeSavedInfo &I : CSI) {
+ unsigned Reg = I.getReg();
+ int FI = I.getFrameIdx();
switch (Reg) {
case ARM::R8:
case ARM::R9:
@@ -1317,11 +1317,11 @@ static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
// Mark the D-register spill slots as properly aligned. Since MFI computes
// stack slot layout backwards, this can actually mean that the d-reg stack
// slot offsets can be wrong. The offset for d8 will always be correct.
- for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
- unsigned DNum = CSI[i].getReg() - ARM::D8;
+ for (const CalleeSavedInfo &I : CSI) {
+ unsigned DNum = I.getReg() - ARM::D8;
if (DNum > NumAlignedDPRCS2Regs - 1)
continue;
- int FI = CSI[i].getFrameIdx();
+ int FI = I.getFrameIdx();
// The even-numbered registers will be 16-byte aligned, the odd-numbered
// registers will be 8-byte aligned.
MFI.setObjectAlignment(FI, DNum % 2 ? Align(8) : Align(16));
@@ -1488,9 +1488,9 @@ static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
// Find the frame index assigned to d8.
int D8SpillFI = 0;
- for (unsigned i = 0, e = CSI.size(); i != e; ++i)
- if (CSI[i].getReg() == ARM::D8) {
- D8SpillFI = CSI[i].getFrameIdx();
+ for (const CalleeSavedInfo &I : CSI)
+ if (I.getReg() == ARM::D8) {
+ D8SpillFI = I.getFrameIdx();
break;
}
diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
index e4e95f63f0a6b..224c61b9f0650 100644
--- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
+++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
@@ -205,9 +205,9 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
return;
}
- for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
- unsigned Reg = CSI[i].getReg();
- int FI = CSI[i].getFrameIdx();
+ for (const CalleeSavedInfo &I : CSI) {
+ unsigned Reg = I.getReg();
+ int FI = I.getFrameIdx();
switch (Reg) {
case ARM::R8:
case ARM::R9:
@@ -266,10 +266,9 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
.addCFIIndex(CFIIndex)
.setMIFlags(MachineInstr::FrameSetup);
}
- for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
- E = CSI.end(); I != E; ++I) {
- unsigned Reg = I->getReg();
- int FI = I->getFrameIdx();
+ for (const CalleeSavedInfo &I : CSI) {
+ unsigned Reg = I.getReg();
+ int FI = I.getFrameIdx();
switch (Reg) {
case ARM::R8:
case ARM::R9:
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index bff596e69efd0..ba97eed082206 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -1404,18 +1404,18 @@ bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB,
// Add callee-saved registers as use.
addCalleeSaveRegistersAsImpOperand(SaveRegsCall, CSI, false, true);
// Add live in registers.
- for (unsigned I = 0; I < CSI.size(); ++I)
- MBB.addLiveIn(CSI[I].getReg());
+ for (const CalleeSavedInfo &I : CSI)
+ MBB.addLiveIn(I.getReg());
return true;
}
- for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
- unsigned Reg = CSI[i].getReg();
+ for (const CalleeSavedInfo &I : CSI) {
+ unsigned Reg = I.getReg();
// Add live in registers. We treat eh_return callee saved register r0 - r3
// specially. They are not really callee saved registers as they are not
// supposed to be killed.
bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg);
- int FI = CSI[i].getFrameIdx();
+ int FI = I.getFrameIdx();
const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI);
if (IsKill)
@@ -1478,10 +1478,10 @@ bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
return true;
}
- for (unsigned i = 0; i < CSI.size(); ++i) {
- unsigned Reg = CSI[i].getReg();
+ for (const CalleeSavedInfo &I : CSI) {
+ unsigned Reg = I.getReg();
const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
- int FI = CSI[i].getFrameIdx();
+ int FI = I.getFrameIdx();
HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI);
}
@@ -1619,8 +1619,8 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
// (1) For each callee-saved register, add that register and all of its
// sub-registers to SRegs.
LLVM_DEBUG(dbgs() << "Initial CS registers: {");
- for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
- unsigned R = CSI[i].getReg();
+ for (const CalleeSavedInfo &I : CSI) {
+ unsigned R = I.getReg();
LLVM_DEBUG(dbgs() << ' ' << printReg(R, TRI));
for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
SRegs[*SR] = true;
@@ -2634,8 +2634,8 @@ bool HexagonFrameLowering::shouldInlineCSR(const MachineFunction &MF,
// Check if CSI only has double registers, and if the registers form
// a contiguous block starting from D8.
BitVector Regs(Hexagon::NUM_TARGET_REGS);
- for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
- unsigned R = CSI[i].getReg();
+ for (const CalleeSavedInfo &I : CSI) {
+ unsigned R = I.getReg();
if (!Hexagon::DoubleRegsRegClass.contains(R))
return true;
Regs[R] = true;
diff --git a/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp b/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp
index a83a5d2dfcc91..2a77a150f9aa1 100644
--- a/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp
@@ -211,8 +211,8 @@ bool MSP430FrameLowering::restoreCalleeSavedRegisters(
MachineFunction &MF = *MBB.getParent();
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
- for (unsigned i = 0, e = CSI.size(); i != e; ++i)
- BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg());
+ for (const CalleeSavedInfo &I : CSI)
+ BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), I.getReg());
return true;
}
diff --git a/llvm/lib/Target/Mips/Mips16FrameLowering.cpp b/llvm/lib/Target/Mips/Mips16FrameLowering.cpp
index fefa1134b0211..622f2039f9e41 100644
--- a/llvm/lib/Target/Mips/Mips16FrameLowering.cpp
+++ b/llvm/lib/Target/Mips/Mips16FrameLowering.cpp
@@ -72,10 +72,9 @@ void Mips16FrameLowering::emitPrologue(MachineFunction &MF,
if (!CSI.empty()) {
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
- for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
- E = CSI.end(); I != E; ++I) {
- int64_t Offset = MFI.getObjectOffset(I->getFrameIdx());
- unsigned Reg = I->getReg();
+ for (const CalleeSavedInfo &I : CSI) {
+ int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
+ unsigned Reg = I.getReg();
unsigned DReg = MRI->getDwarfRegNum(Reg, true);
unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, DReg, Offset));
@@ -119,13 +118,13 @@ bool Mips16FrameLowering::spillCalleeSavedRegisters(
// will be saved with the "save" instruction
// during emitPrologue
//
- for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
+ for (const CalleeSavedInfo &I : CSI) {
// Add the callee-saved register as live-in. Do not add if the register is
// RA and return address is taken, because it has already been added in
// method MipsTargetLowering::lowerRETURNADDR.
// It's killed at the spill, unless the register is RA and return address
// is taken.
- unsigned Reg = CSI[i].getReg();
+ unsigned Reg = I.getReg();
bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA)
&& MF->getFrameInfo().isReturnAddressTaken();
if (!IsRAAndRetAddrIsTaken)
diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
index bb4b9c6fa6a72..193d071447ff3 100644
--- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -452,10 +452,9 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
// Iterate over list of callee-saved registers and emit .cfi_offset
// directives.
- for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
- E = CSI.end(); I != E; ++I) {
- int64_t Offset = MFI.getObjectOffset(I->getFrameIdx());
- unsigned Reg = I->getReg();
+ for (const CalleeSavedInfo &I : CSI) {
+ int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
+ unsigned Reg = I.getReg();
// If Reg is a double precision register, emit two cfa_offsets,
// one for each of the paired single precision registers.
@@ -796,13 +795,13 @@ bool MipsSEFrameLowering::spillCalleeSavedRegisters(
MachineFunction *MF = MBB.getParent();
const TargetInstrInfo &TII = *STI.getInstrInfo();
- for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
+ for (const CalleeSavedInfo &I : CSI) {
// Add the callee-saved register as live-in. Do not add if the register is
// RA and return address is taken, because it has already been added in
// method MipsTargetLowering::lowerRETURNADDR.
// It's killed at the spill, unless the register is RA and return address
// is taken.
- unsigned Reg = CSI[i].getReg();
+ unsigned Reg = I.getReg();
bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
&& MF->getFrameInfo().isReturnAddressTaken();
if (!IsRAAndRetAddrIsTaken)
@@ -831,8 +830,7 @@ bool MipsSEFrameLowering::spillCalleeSavedRegisters(
// Insert the spill to the stack frame.
bool IsKill = !IsRAAndRetAddrIsTaken;
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
- TII.storeRegToStackSlot(MBB, MI, Reg, IsKill,
- CSI[i].getFrameIdx(), RC, TRI);
+ TII.storeRegToStackSlot(MBB, MI, Reg, IsKill, I.getFrameIdx(), RC, TRI);
}
return true;
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