[llvm] eced446 - [Thumb2] Regenerate ext + rot tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 21 10:33:51 PST 2021
Author: Simon Pilgrim
Date: 2021-11-21T18:33:28Z
New Revision: eced44637cfbfda462888255ac812ad48544f7de
URL: https://github.com/llvm/llvm-project/commit/eced44637cfbfda462888255ac812ad48544f7de
DIFF: https://github.com/llvm/llvm-project/commit/eced44637cfbfda462888255ac812ad48544f7de.diff
LOG: [Thumb2] Regenerate ext + rot tests
Added:
Modified:
llvm/test/CodeGen/Thumb2/thumb2-sxt_rot.ll
llvm/test/CodeGen/Thumb2/thumb2-uxt_rot.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Thumb2/thumb2-sxt_rot.ll b/llvm/test/CodeGen/Thumb2/thumb2-sxt_rot.ll
index c4af67a2f91d0..fe40113d7e703 100644
--- a/llvm/test/CodeGen/Thumb2/thumb2-sxt_rot.ll
+++ b/llvm/test/CodeGen/Thumb2/thumb2-sxt_rot.ll
@@ -1,21 +1,24 @@
-; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s %s -o - | FileCheck %s --check-prefix=CHECK-DSP
-; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefix=CHECK-NO-DSP
-; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK-DSP
-; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK-NO-DSP
-; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK-DSP
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-DSP
+; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-DSP
+; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-DSP
+; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-NO-DSP
+; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-DSP
define i32 @test0(i8 %A) {
; CHECK-LABEL: test0:
-; CHECK-DSP: sxtb r0, r0
-; CHECK-NO-DSP: sxtb r0, r0
- %B = sext i8 %A to i32
+; CHECK: @ %bb.0:
+; CHECK-NEXT: sxtb r0, r0
+; CHECK-NEXT: bx lr
+ %B = sext i8 %A to i32
ret i32 %B
}
define signext i8 @test1(i32 %A) {
; CHECK-LABEL: test1:
-; CHECK-DSP: sbfx r0, r0, #8, #8
-; CHECK-NO-DSP: sbfx r0, r0, #8, #8
+; CHECK: @ %bb.0:
+; CHECK-NEXT: sbfx r0, r0, #8, #8
+; CHECK-NEXT: bx lr
%B = lshr i32 %A, 8
%C = shl i32 %A, 24
%D = or i32 %B, %C
@@ -24,22 +27,36 @@ define signext i8 @test1(i32 %A) {
}
define signext i32 @test2(i32 %A, i32 %X) {
-; CHECK-LABEL: test2:
-; CHECK-DSP: sxtab r0, r1, r0, ror #8
-; CHECK-NO-DSP-NOT: sxtab
+; CHECK-DSP-LABEL: test2:
+; CHECK-DSP: @ %bb.0:
+; CHECK-DSP-NEXT: sxtab r0, r1, r0, ror #8
+; CHECK-DSP-NEXT: bx lr
+;
+; CHECK-NO-DSP-LABEL: test2:
+; CHECK-NO-DSP: @ %bb.0:
+; CHECK-NO-DSP-NEXT: sbfx r0, r0, #8, #8
+; CHECK-NO-DSP-NEXT: add r0, r1
+; CHECK-NO-DSP-NEXT: bx lr
%B = lshr i32 %A, 8
%C = shl i32 %A, 24
%D = or i32 %B, %C
%E = trunc i32 %D to i8
- %F = sext i8 %E to i32
- %G = add i32 %F, %X
+ %F = sext i8 %E to i32
+ %G = add i32 %F, %X
ret i32 %G
}
define i32 @test3(i32 %A, i32 %X) {
-; CHECK-LABEL: test3:
-; CHECK-DSP: sxtah r0, r0, r1, ror #8
-; CHECK-NO-DSP-NOT: sxtah
+; CHECK-DSP-LABEL: test3:
+; CHECK-DSP: @ %bb.0:
+; CHECK-DSP-NEXT: sxtah r0, r0, r1, ror #8
+; CHECK-DSP-NEXT: bx lr
+;
+; CHECK-NO-DSP-LABEL: test3:
+; CHECK-NO-DSP: @ %bb.0:
+; CHECK-NO-DSP-NEXT: sbfx r1, r1, #8, #16
+; CHECK-NO-DSP-NEXT: add r0, r1
+; CHECK-NO-DSP-NEXT: bx lr
%X.hi = lshr i32 %X, 8
%X.trunc = trunc i32 %X.hi to i16
%addend = sext i16 %X.trunc to i32
@@ -48,9 +65,16 @@ define i32 @test3(i32 %A, i32 %X) {
}
define signext i32 @test4(i32 %A, i32 %X) {
-; CHECK-LABEL: test4:
-; CHECK-DSP: sxtab r0, r1, r0, ror #16
-; CHECK-NO-DSP-NOT: sxtab
+; CHECK-DSP-LABEL: test4:
+; CHECK-DSP: @ %bb.0:
+; CHECK-DSP-NEXT: sxtab r0, r1, r0, ror #16
+; CHECK-DSP-NEXT: bx lr
+;
+; CHECK-NO-DSP-LABEL: test4:
+; CHECK-NO-DSP: @ %bb.0:
+; CHECK-NO-DSP-NEXT: sbfx r0, r0, #16, #8
+; CHECK-NO-DSP-NEXT: add r0, r1
+; CHECK-NO-DSP-NEXT: bx lr
%B = lshr i32 %A, 16
%C = shl i32 %A, 16
%D = or i32 %B, %C
@@ -61,14 +85,21 @@ define signext i32 @test4(i32 %A, i32 %X) {
}
define signext i32 @test5(i32 %A, i32 %X) {
-; CHECK-LABEL: test5:
-; CHECK-DSP: sxtah r0, r1, r0, ror #24
-; CHECK-NO-DSP-NOT: sxtah
+; CHECK-DSP-LABEL: test5:
+; CHECK-DSP: @ %bb.0:
+; CHECK-DSP-NEXT: sxtah r0, r1, r0, ror #24
+; CHECK-DSP-NEXT: bx lr
+;
+; CHECK-NO-DSP-LABEL: test5:
+; CHECK-NO-DSP: @ %bb.0:
+; CHECK-NO-DSP-NEXT: sxth.w r0, r0, ror #24
+; CHECK-NO-DSP-NEXT: add r0, r1
+; CHECK-NO-DSP-NEXT: bx lr
%B = lshr i32 %A, 24
%C = shl i32 %A, 8
%D = or i32 %B, %C
%E = trunc i32 %D to i16
- %F = sext i16 %E to i32
- %G = add i32 %F, %X
+ %F = sext i16 %E to i32
+ %G = add i32 %F, %X
ret i32 %G
}
diff --git a/llvm/test/CodeGen/Thumb2/thumb2-uxt_rot.ll b/llvm/test/CodeGen/Thumb2/thumb2-uxt_rot.ll
index 22740b715dcb1..413f6916f231c 100644
--- a/llvm/test/CodeGen/Thumb2/thumb2-uxt_rot.ll
+++ b/llvm/test/CodeGen/Thumb2/thumb2-uxt_rot.ll
@@ -1,22 +1,31 @@
-; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s --check-prefix=CHECK-DSP
-; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefix=CHECK-NO-DSP
-; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK-DSP
-; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK-NO-DSP
-; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK-DSP
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-DSP
+; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-DSP
+; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-DSP
+; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-NO-DSP
+; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-DSP
; rdar://11318438
define zeroext i8 @test1(i32 %A.u) {
; CHECK-LABEL: test1:
-; CHECK-DSP: uxtb r0, r0
-; CHECK-NO-DSP: uxtb r0, r0
+; CHECK: @ %bb.0:
+; CHECK-NEXT: uxtb r0, r0
+; CHECK-NEXT: bx lr
%B.u = trunc i32 %A.u to i8
ret i8 %B.u
}
define zeroext i32 @test2(i32 %A.u, i32 %B.u) {
-; CHECK-LABEL: test2:
-; CHECK-DSP: uxtab r0, r0, r1
-; CHECK-NO-DSP-NOT: uxtab
+; CHECK-DSP-LABEL: test2:
+; CHECK-DSP: @ %bb.0:
+; CHECK-DSP-NEXT: uxtab r0, r0, r1
+; CHECK-DSP-NEXT: bx lr
+;
+; CHECK-NO-DSP-LABEL: test2:
+; CHECK-NO-DSP: @ %bb.0:
+; CHECK-NO-DSP-NEXT: uxtb r1, r1
+; CHECK-NO-DSP-NEXT: add r0, r1
+; CHECK-NO-DSP-NEXT: bx lr
%C.u = trunc i32 %B.u to i8
%D.u = zext i8 %C.u to i32
%E.u = add i32 %A.u, %D.u
@@ -25,8 +34,9 @@ define zeroext i32 @test2(i32 %A.u, i32 %B.u) {
define zeroext i32 @test3(i32 %A.u) {
; CHECK-LABEL: test3:
-; CHECK-DSP: ubfx r0, r0, #8, #16
-; CHECK-NO-DSP: ubfx r0, r0, #8, #16
+; CHECK: @ %bb.0:
+; CHECK-NEXT: ubfx r0, r0, #8, #16
+; CHECK-NEXT: bx lr
%B.u = lshr i32 %A.u, 8
%C.u = shl i32 %A.u, 24
%D.u = or i32 %B.u, %C.u
@@ -36,9 +46,16 @@ define zeroext i32 @test3(i32 %A.u) {
}
define i32 @test4(i32 %A, i32 %X) {
-; CHECK-LABEL: test4:
-; CHECK-DSP: uxtab r0, r0, r1, ror #16
-; CHECK-NO-DSP-NOT: uxtab
+; CHECK-DSP-LABEL: test4:
+; CHECK-DSP: @ %bb.0:
+; CHECK-DSP-NEXT: uxtab r0, r0, r1, ror #16
+; CHECK-DSP-NEXT: bx lr
+;
+; CHECK-NO-DSP-LABEL: test4:
+; CHECK-NO-DSP: @ %bb.0:
+; CHECK-NO-DSP-NEXT: ubfx r1, r1, #16, #8
+; CHECK-NO-DSP-NEXT: add r0, r1
+; CHECK-NO-DSP-NEXT: bx lr
%X.hi = lshr i32 %X, 16
%X.trunc = trunc i32 %X.hi to i8
%addend = zext i8 %X.trunc to i32
@@ -47,9 +64,16 @@ define i32 @test4(i32 %A, i32 %X) {
}
define i32 @test5(i32 %A, i32 %X) {
-; CHECK-LABEL: test5:
-; CHECK-DSP: uxtah r0, r0, r1, ror #8
-; CHECK-NO-DSP-NOT: uxtah
+; CHECK-DSP-LABEL: test5:
+; CHECK-DSP: @ %bb.0:
+; CHECK-DSP-NEXT: uxtah r0, r0, r1, ror #8
+; CHECK-DSP-NEXT: bx lr
+;
+; CHECK-NO-DSP-LABEL: test5:
+; CHECK-NO-DSP: @ %bb.0:
+; CHECK-NO-DSP-NEXT: ubfx r1, r1, #8, #16
+; CHECK-NO-DSP-NEXT: add r0, r1
+; CHECK-NO-DSP-NEXT: bx lr
%X.hi = lshr i32 %X, 8
%X.trunc = trunc i32 %X.hi to i16
%addend = zext i16 %X.trunc to i32
@@ -58,9 +82,16 @@ define i32 @test5(i32 %A, i32 %X) {
}
define i32 @test6(i32 %A, i32 %X) {
-; CHECK-LABEL: test6:
-; CHECK-DSP: uxtab r0, r0, r1, ror #8
-; CHECK-NO-DSP-NOT: uxtab
+; CHECK-DSP-LABEL: test6:
+; CHECK-DSP: @ %bb.0:
+; CHECK-DSP-NEXT: uxtab r0, r0, r1, ror #8
+; CHECK-DSP-NEXT: bx lr
+;
+; CHECK-NO-DSP-LABEL: test6:
+; CHECK-NO-DSP: @ %bb.0:
+; CHECK-NO-DSP-NEXT: ubfx r1, r1, #8, #8
+; CHECK-NO-DSP-NEXT: add r0, r1
+; CHECK-NO-DSP-NEXT: bx lr
%X.hi = lshr i32 %X, 8
%X.trunc = trunc i32 %X.hi to i8
%addend = zext i8 %X.trunc to i32
@@ -69,9 +100,17 @@ define i32 @test6(i32 %A, i32 %X) {
}
define i32 @test7(i32 %A, i32 %X) {
-; CHECK-LABEL: test7:
-; CHECK-DSP: uxtah r0, r0, r1, ror #24
-; CHECK-NO-DSP-NOT: uxtah
+; CHECK-DSP-LABEL: test7:
+; CHECK-DSP: @ %bb.0:
+; CHECK-DSP-NEXT: uxtah r0, r0, r1, ror #24
+; CHECK-DSP-NEXT: bx lr
+;
+; CHECK-NO-DSP-LABEL: test7:
+; CHECK-NO-DSP: @ %bb.0:
+; CHECK-NO-DSP-NEXT: ror.w r1, r1, #24
+; CHECK-NO-DSP-NEXT: uxth r1, r1
+; CHECK-NO-DSP-NEXT: add r0, r1
+; CHECK-NO-DSP-NEXT: bx lr
%lshr = lshr i32 %X, 24
%shl = shl i32 %X, 8
%or = or i32 %lshr, %shl
@@ -82,9 +121,17 @@ define i32 @test7(i32 %A, i32 %X) {
}
define i32 @test8(i32 %A, i32 %X) {
-; CHECK-LABEL: test8:
-; CHECK-DSP: uxtah r0, r0, r1, ror #24
-; CHECK-NO-DSP-NOT: uxtah
+; CHECK-DSP-LABEL: test8:
+; CHECK-DSP: @ %bb.0:
+; CHECK-DSP-NEXT: uxtah r0, r0, r1, ror #24
+; CHECK-DSP-NEXT: bx lr
+;
+; CHECK-NO-DSP-LABEL: test8:
+; CHECK-NO-DSP: @ %bb.0:
+; CHECK-NO-DSP-NEXT: ror.w r1, r1, #24
+; CHECK-NO-DSP-NEXT: uxth r1, r1
+; CHECK-NO-DSP-NEXT: add r0, r1
+; CHECK-NO-DSP-NEXT: bx lr
%lshr = lshr i32 %X, 24
%shl = shl i32 %X, 8
%or = or i32 %lshr, %shl
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