[PATCH] D114315: [X86][Costmodel] `getReplicationShuffleCost()`: promote 1 bit-wide elements to 32 bit when have AVX512DQ

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri created this revision.
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I believe, this effectively completes `X86TTIImpl::getReplicationShuffleCost()`
for AVX512, other than the question of handling plain AVX512F,
where we end up with some really ugly "shuffles",
but then is there any CPU's that support AVX512, but not AVX512DQ/AVX512BW?


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D114315

Files:
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/X86/shuffle-replication-i1.ll

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