[PATCH] D114257: [AMDGPU] Enable fneg and fabs divergence-driven instruction selection.

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:1509
   (fabs (f32 VGPR_32:$src)),
   (V_AND_B32_e32 (S_MOV_B32 (i32 0x7fffffff)), VGPR_32:$src)
 >;
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I think all of that should use VOP3 forms. That way you will avoid copy from SGPR to VGPR which appears in your test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114257/new/

https://reviews.llvm.org/D114257