[PATCH] D114257: [AMDGPU] Enable fneg and fabs divergence-deriven instruction selection.

[Alexander via Phabricator via llvm-commits]

alex-t created this revision.
alex-t added reviewers: rampitec, arsenm.
Herald added subscribers: foad, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
alex-t requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.

Detailed description: We currently have a set of patterns to select ISD::FNEG

  and ISD::FABS to the bitwise operations.  We need to make them predicated to
  select the VALU or SALU bitwise operation variant according to the SDNode
  divergence bit.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D114257

Files:
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
  llvm/test/CodeGen/AMDGPU/fabs.f64.ll
  llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll
  llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
  llvm/test/CodeGen/AMDGPU/fneg.f64.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D114257.388530.patch
Type: text/x-patch
Size: 42486 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20211119/799d2c52/attachment.bin>