[PATCH] D114230: [AMDGPU] Use new opcode for indexed vgpr reads

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/VOP1Instructions.td:870-871
                                         getVOPSrc0ForVT<i32>.ret:$src0)> {
   let VOP1 = 1;
   let SubtargetPredicate = isGFX8GFX9;
 }
----------------
arsenm wrote:
> Probably should be a separate patch, but should these have implicit m0 reads (and maybe hasSideEffects = 1?)
> Probably should be a separate patch, but should these have implicit m0 reads

D114239.

> and maybe hasSideEffects = 1?

That doesn't seem necessary. Do these instructions have any side effects that aren't adequately modelled by the implicit operands?


Repository:
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  https://reviews.llvm.org/D114230/new/

https://reviews.llvm.org/D114230