[PATCH] D114239: [AMDGPU] Add an implicit use of M0 to all V_MOV_B32_indirect_read/write

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
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NFCI. Previously the implicit use was added to V_MOV_B32_indirect_read
when building the instruction. V_MOV_B32_indirect_write didn't have an
implicit use of M0 at all, but apparently it did not cause any problems.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D114239

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/VOP1Instructions.td
  llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir

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