[PATCH] D114200: [D114198] precommit regen mir tests part 1

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic created this revision.
Herald added subscribers: kerbowa, nhaehnle, jvesely.
Petar.Avramovic requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

https://reviews.llvm.org/D114200

Files:
  llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usube.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir